FallenSigh
ae5f0ca048
Phase 3.2: Verifies module chaining works. - sha3_chain_top.v: 3-state FSM (IDLE→BUSY→DONE), feeds d_in→sha3_top(G) - Captures rho[255:0] and sigma[511:256] from SHA3-512 output - Verified: 3/3 bit-exact vs Python G(d||k=2) reference KG full-path FSM (~11 module chain) deferred — too complex for single dispatch.
94 lines
2.8 KiB
Verilog
94 lines
2.8 KiB
Verilog
// sha3_chain_top.v - Simple integration module: d → SHA3_G(d||k=2)
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//
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// Feeds external 256-bit d to sha3_top in G mode with k=2, captures
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// rho (first 256 bits) and sigma (next 256 bits) from the hash output.
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//
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// 3-state FSM: IDLE → BUSY → DONE
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//
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// Interface:
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// clk, rst_n - clock, active-low reset
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// d_in[255:0] - 256-bit d input (external, NOT from RNG)
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// start_i - start computation
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// done_o - computation complete
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// rho_out - G output first 256 bits
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// sigma_out - G output next 256 bits
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module sha3_chain_top (
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input clk,
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input rst_n,
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input [255:0] d_in,
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input start_i,
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output done_o,
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output [255:0] rho_out,
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output [255:0] sigma_out
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);
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localparam ST_IDLE = 2'd0;
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localparam ST_BUSY = 2'd1;
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localparam ST_DONE = 2'd2;
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reg [1:0] state_r, state_next;
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// ── sha3_top signals ──
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wire [511:0] sha3_data_i;
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wire sha3_valid_i;
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wire sha3_ready_o;
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wire [511:0] sha3_hash_o;
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wire sha3_valid_o;
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// data_i = {248'b0, k=8'd2, d_in}
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assign sha3_data_i = {248'b0, 8'd2, d_in};
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sha3_top u_sha3 (
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.clk (clk),
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.rst_n (rst_n),
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.mode (2'b00), // G mode (SHA3-512)
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.data_i (sha3_data_i),
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.valid_i (sha3_valid_i),
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.ready_o (sha3_ready_o),
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.hash_o (sha3_hash_o),
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.valid_o (sha3_valid_o),
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.ready_i (1'b1) // always accept output
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);
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// valid_i: assert when IDLE + start_i + sha3 ready
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assign sha3_valid_i = (state_r == ST_IDLE) && start_i && sha3_ready_o;
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// done_o
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assign done_o = (state_r == ST_DONE);
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// ── output registers ──
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reg [255:0] rho_out_r, sigma_out_r;
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assign rho_out = rho_out_r;
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assign sigma_out = sigma_out_r;
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// ── FSM combinational next-state ──
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always @(*) begin
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state_next = state_r;
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case (state_r)
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ST_IDLE: if (start_i && sha3_ready_o) state_next = ST_BUSY;
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ST_BUSY: if (sha3_valid_o) state_next = ST_DONE;
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ST_DONE: if (!start_i) state_next = ST_IDLE;
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default: state_next = ST_IDLE;
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endcase
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end
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// ── sequential logic ──
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state_r <= ST_IDLE;
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rho_out_r <= 256'd0;
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sigma_out_r <= 256'd0;
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end else begin
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state_r <= state_next;
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// Capture output when BUSY → DONE
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if (state_r == ST_BUSY && sha3_valid_o) begin
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rho_out_r <= sha3_hash_o[255:0];
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sigma_out_r <= sha3_hash_o[511:256];
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end
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end
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end
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endmodule
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