FallenSigh
a369a421b7
Phase 3.1 + 3.3: - sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM) - s_bram.v: single-port RAM (rd_en/wr_en, write priority) - comp_decomp_sync.v: streaming compress/decompress with round-half-up Verified: storage 5/5, comp_decomp 60/60 all PASS
33 lines
884 B
Verilog
33 lines
884 B
Verilog
// sd_bram.v - Simple dual-port behavioral RAM (1 read + 1 write port)
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//
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// Vivado auto-infers this as BRAM when W >= 12 and D >= 64.
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// Read: rd_addr sampled at posedge → rd_addr_r → rd_data = mem[rd_addr_r]
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// Write: wr_data written to mem[wr_addr] at posedge when wr_en=1
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// No valid/ready handshake — pure combinational-read / registered-write memory.
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module sd_bram #(
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parameter W = 48,
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parameter D = 64,
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parameter A = 6
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) (
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input wire clk,
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input wire [A-1:0] rd_addr,
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output wire [W-1:0] rd_data,
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input wire wr_en,
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input wire [A-1:0] wr_addr,
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input wire [W-1:0] wr_data
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);
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reg [W-1:0] mem [0:D-1];
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reg [A-1:0] rd_addr_r;
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always @(posedge clk) begin
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rd_addr_r <= rd_addr;
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if (wr_en)
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mem[wr_addr] <= wr_data;
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end
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assign rd_data = mem[rd_addr_r];
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endmodule
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