FallenSigh 2fb1cd67e3 revert comp_decomp_sync.v

2026-06-30 03:17:55 +08:00

..

common

fix(rtl,scripts): replace combinational divider with Barrett multiplication, add synthesis include_dirs, set 50MHz clock

2026-06-30 00:23:43 +08:00

comp_decomp

revert comp_decomp_sync.v

2026-06-30 03:17:55 +08:00

ntt

fix(rtl): add use_dsp="no" attributes, fix duplicate wire declaration

2026-06-29 23:23:58 +08:00

poly_arith

chore(tb): remove Verilator TBs + framework; parallelize XSIM runs

2026-06-29 16:05:06 +08:00

poly_mul

chore(tb): remove Verilator TBs + framework; parallelize XSIM runs

2026-06-29 16:05:06 +08:00

rng

chore(tb): remove Verilator TBs + framework; parallelize XSIM runs

2026-06-29 16:05:06 +08:00

sample_cbd

chore(tb): remove Verilator TBs + framework; parallelize XSIM runs

2026-06-29 16:05:06 +08:00

sample_ntt

fix(rtl): add use_dsp="no" attributes, fix duplicate wire declaration

2026-06-29 23:23:58 +08:00

sha3

chore(tb): remove Verilator TBs + framework; parallelize XSIM runs

2026-06-29 16:05:06 +08:00

storage

chore(tb): remove Verilator TBs + framework; parallelize XSIM runs

2026-06-29 16:05:06 +08:00

top

fix(rtl): add use_dsp="no" attributes, fix duplicate wire declaration

2026-06-29 23:23:58 +08:00