FallenSigh
a369a421b7
Phase 3.1 + 3.3: - sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM) - s_bram.v: single-port RAM (rd_en/wr_en, write priority) - comp_decomp_sync.v: streaming compress/decompress with round-half-up Verified: storage 5/5, comp_decomp 60/60 all PASS
32 lines
855 B
Verilog
32 lines
855 B
Verilog
// s_bram.v - Single-port behavioral RAM (shared read/write port)
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//
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// One port: either read or write per cycle (+1 cycle read latency).
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// When both rd_en and wr_en are high, write takes priority.
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// Read data is registered (1-cycle latency after rd_en).
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// No valid/ready handshake — pure memory, handshake managed at higher level.
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module s_bram #(
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parameter W = 48,
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parameter D = 512,
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parameter A = 9
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) (
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input wire clk,
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input wire rd_en,
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input wire [A-1:0] rd_addr,
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output reg [W-1:0] rd_data,
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input wire wr_en,
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input wire [A-1:0] wr_addr,
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input wire [W-1:0] wr_data
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);
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reg [W-1:0] mem [0:D-1];
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always @(posedge clk) begin
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if (wr_en)
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mem[wr_addr] <= wr_data;
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else if (rd_en)
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rd_data <= mem[rd_addr];
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end
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endmodule
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