FallenSigh
209ca90fb1
Phase 2.3: Polynomial modular addition and subtraction. - poly_arith_sync.v: mode=0 add (a+b mod Q), mode=1 sub (a-b mod Q) - Pure streaming (1 coeff/cycle, no BRAM needed) - Uses pipeline_reg for valid/ready handshake Verified: 10/10 vectors bit-exact vs Python reference
62 lines
2.1 KiB
Verilog
62 lines
2.1 KiB
Verilog
// poly_arith_sync.v - Polynomial modular add/sub for ML-KEM
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//
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// Performs element-wise modular addition or subtraction on two streaming
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// 256-coefficient polynomials over Z_q (q=3329).
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//
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// mode=0: coeff_out = (coeff_a_in + coeff_b_in) mod Q
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// mode=1: coeff_out = (coeff_a_in - coeff_b_in) mod Q
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//
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// Each cycle processes one coefficient pair. Pure streaming — no internal
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// storage; the caller sequences all 256 coefficients in order.
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`include "sync_rtl/common/defines.vh"
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module poly_arith_sync (
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input clk,
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input rst_n,
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input [11:0] coeff_a_in,
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input [11:0] coeff_b_in,
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input mode, // 0=add, 1=sub
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input valid_i,
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output ready_o,
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output [11:0] coeff_out,
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output valid_o,
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input ready_i
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);
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//--------------------------------------------------------------
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// Combinational modular arithmetic
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//--------------------------------------------------------------
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wire [12:0] add_raw; // a + b (13-bit to catch overflow)
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wire [11:0] add_sub_q; // (a + b) - Q
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wire [11:0] add_result; // (a + b) mod Q
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assign add_raw = {1'b0, coeff_a_in} + {1'b0, coeff_b_in};
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assign add_sub_q = add_raw[11:0] - `Q;
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assign add_result = (add_raw < `Q) ? add_raw[11:0] : add_sub_q;
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wire [11:0] sub_result; // (a - b) mod Q
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// When a >= b: diff = a - b (already in [0, Q-2])
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// When a < b: diff = a + Q - b (borrow correction)
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assign sub_result = (coeff_a_in < coeff_b_in)
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? (coeff_a_in + `Q - coeff_b_in)
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: (coeff_a_in - coeff_b_in);
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wire [11:0] mod_result = mode ? sub_result : add_result;
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//--------------------------------------------------------------
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// Pipeline the result through pipeline_reg for valid/ready
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//--------------------------------------------------------------
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pipeline_reg #(.DW(12)) u_pipe (
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.clk (clk),
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.rst_n (rst_n),
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.data_i (mod_result),
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.valid_i(valid_i),
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.ready_o(ready_o),
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.data_o (coeff_out),
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.valid_o(valid_o),
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.ready_i(ready_i)
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);
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endmodule
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