FallenSigh
c4cd10c2c1
Phase 2.1: Merged Path00+Path01 NTT engine. - barrett_mul.v: Barrett modular multiplication (a·b mod 3329) - butterfly_unit.v: Cooley-Tukey/Gentleman-Sande butterfly - zeta_rom.v: 128-entry ROM with bit-reversed roots of unity - ntt_core.v: 7-layer NTT FSM, 256×12-bit register file - ntt_sync.v: valid/ready streaming wrapper Verified: 13/13 vectors bit-exact vs Python NTT/NTTInverse
20 lines
523 B
Verilog
20 lines
523 B
Verilog
module ntt_sync (
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input clk, rst_n,
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input [11:0] coeff_in,
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input valid_i,
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output ready_o,
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output [11:0] coeff_out,
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output valid_o,
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input ready_i,
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input mode,
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output done_o
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);
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ntt_core u_ntt_core (
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.clk(clk), .rst_n(rst_n),
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.coeff_in(coeff_in), .valid_i(valid_i), .ready_o(ready_o),
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.mode(mode),
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.coeff_out(coeff_out), .valid_o(valid_o), .ready_i(ready_i),
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.done_o(done_o)
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);
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endmodule
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