FallenSigh
8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
74 lines
2.3 KiB
Verilog
74 lines
2.3 KiB
Verilog
// skid_buffer.v - 2-entry skid buffer with valid/ready handshake
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//
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// When valid_i && ready_o, capture data_i. Output via valid_o && ready_i.
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// Stores one extra entry in skid register. Pure combinational ready_o path.
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//
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// Parameters:
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// DW = data width (default 12)
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//
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// Interface:
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// clk, rst_n - clock, active-low reset
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// data_i, valid_i, ready_o - input side
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// data_o, valid_o, ready_i - output side
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module skid_buffer #(parameter DW = 12) (
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input clk,
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input rst_n,
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input [DW-1:0] data_i,
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input valid_i,
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output ready_o,
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output [DW-1:0] data_o,
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output valid_o,
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input ready_i
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);
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// Internal state
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reg skid_valid; // skid register has valid data
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reg [DW-1:0] skid_data; // skid register data
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// Output register (pipeline stage)
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reg out_valid;
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reg [DW-1:0] out_data;
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// ready_o is combinational: ready when output slot is empty
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// (either out_valid is 0, or ready_i is high and we can accept new data)
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assign ready_o = !out_valid || ready_i;
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// valid_o drives from output register
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assign valid_o = out_valid;
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assign data_o = out_data;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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skid_valid <= 1'b0;
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skid_data <= {DW{1'b0}};
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out_valid <= 1'b0;
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out_data <= {DW{1'b0}};
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end else begin
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if (out_valid && ready_i) begin
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// Output consumed: load from skid if available
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if (skid_valid) begin
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out_data <= skid_data;
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out_valid <= 1'b1;
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skid_valid <= 1'b0;
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end else begin
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out_valid <= 1'b0;
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end
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end
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if (valid_i && ready_o) begin
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if (!out_valid || (out_valid && ready_i && !skid_valid)) begin
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// Output slot free: go directly to output
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out_data <= data_i;
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out_valid <= 1'b1;
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end else begin
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// Output slot occupied: store in skid
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skid_data <= data_i;
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skid_valid <= 1'b1;
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end
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end
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end
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end
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endmodule
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