FallenSigh
717a9929b6
- Replace / and % operators in comp_decomp_sync with Barrett multiply-by-reciprocal (dividend * 5039 >> 24) + correction step. Eliminates ~100 CARRY4 divider chain. - Add include_dirs for sources_1 fileset so Windows Vivado synthesis finds defines.vh. - Change CLK_PERIOD from 10.0 (100MHz) to 40.0 (50MHz) to reflect actual target.
7 lines
174 B
Systemverilog
7 lines
174 B
Systemverilog
`ifndef DEFINES_VH
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`define DEFINES_VH
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`define CLK_PERIOD 20.0 // 50MHz
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`define Q 3329 // ML-KEM prime modulus
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`define N 256 // polynomial degree
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`endif
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