test(top): two-instance hello_world TB (genenc + dec split)

Add tb_mlkem_two_inst_xsim: runs the hello_world protocol across TWO mlkem_top
instances, modeling the real two-party split:
  * u_genenc: KeyGen THEN Encaps on one instance. KeyGen writes ek into its own
    ek_bram and Encaps reuses it directly (no re-streaming) -> shared_key, ct.
  * u_dec: Decaps on a separate instance, receiving dk + ct streamed over from
    u_genenc via the input ports.

Verifies A.shared_key == B.recovered_key and 'hello world' round-trips. Output
matches the single-instance TB and the Rust reference (key=ced0c031a4bee34a...).

run_hello.sh gains a 'two' arg to select this TB; default stays single-instance.

.claude/plans/decaps_plan.md

@@ -62,16 +62,16 @@
 
 ## 实现阶段(逐阶段 dbg/KAT 对拍)
 - **D0 — 脚手架 + dk/c 载入 + 解析** ✅:op_i 加宽 2-bit(00 KG/01 Enc/10 Dec),ST_DEC_LOAD(D0 暂直接→DONE)。dk 流入按 region 路由:dk_pke→dkp_bram、ek_pke→ek_bram、h→hek_r、z→z_r;ct→c_in_bram(独立于 ct_bram)。dbg 验证 h/z/ek_pke/dk_pke。**踩坑1:载入路由用 k_r 但 k_r 在 start_i 才锁存 → 预载期 region 边界全 0,路由全错。改用 LIVE k_i 边界(dkp_bytes_ld 等)。踩坑2:旧 KG/Enc TB 未接新端口(dk_in_*/c_in_*/dbg_*)→ X 漂入 write mux,KeyGen/Encaps 超时回归。补 tie-off 0。** runner = `./run_tb.sh dec [K] [CASE]`。K=2/3/4 D0 全过,KG/Enc 回归通过。
-- **D1 — byteDecode_d + Decompress → u'/v'**:新解包器 + comp_decomp mode=1。dbg 对 u'/v'(ml-kem-r golden,新 dump_decaps)。
+- **D1 — byteDecode_d + Decompress → u'/v'** ✅:复用 comp_decomp(改 mode 可选:Encaps C1/C2 compress mode=0,Decaps DECOMP mode=1)。ST_DEC_DECOMP 内联 byteDecode 走子机:逐字节读 c_in_bram,LSB-first 累进 bit buffer,凑够 d 位抽符号→comp_decomp 解压→写 bank。c1(K 多项式,d=du)→u'[i] bank_se rel i;c2(1 多项式,d=dv)→v' bank_t rel DEC_VSLOT=2(避开 UPSUM=1)。dbg_slot_i 加宽 4→6 bit(K=4 v' 在 slot 26)。dump_decaps.rs(ml-kem-r 工作树)产 u'/v'/s_hat/u_hat/w/m' golden 到 vectors/decgold/。**踩坑:dbg coeff 读回延迟 = bank(1)+dbg_coeff_r(1),TB rdcoeff 等 2 拍少一拍 → 数据整体错位一格;改 3 拍修正。** K=2/3/4 全过,KG/Enc 回归通过。
-- **D2 — s_hat 解码 + u_hat = NTT(u')**:TDEC 复用(dk_pke 源)、ntt_core fwd。dbg 对 s_hat / u_hat。
+- **D2 — s_hat 解码 + u_hat = NTT(u')** ✅:复用 Encaps TDEC 机(ST_DEC_SDEC),字节源从 ek 切到 dkp_bram(td_byte mux + dkp_rd_addr 在 SDEC 走 td_ekaddr),s_hat 写 bank_a slot j*K(与 t_hat 同布局,D3 MAC 可直接读)。复用前向 NTT 机(ST_DEC_NTT,n_slot_max=k_r)对 bank_se rel 0..K-1 的 u' 原地变换成 u_hat。**踩坑:NTT 原地覆盖 u' → verify_d1 复查 u' 必失败;改为 verify_d1 只查 v'(bank_t 未动),u' 正确性由 u_hat==NTT(u') golden 传递性证明。** K=2/3/4 全过,KG/Enc 回归通过。
-- **D3 — w = v' − INTT(Σ s∘u_hat)**:V 机器 SUB 变体。dbg 对 w。
+- **D3 — w = v' − INTT(Σ s∘u_hat)** ✅:复用 Encaps V 机(ST_DEC_W,u_row=0 单多项式)。MAC s_hat[j](bank_a slot j*K)∘ u_hat[j](bank_se rel j)→psum bank_t[UPSUM],与 V MAC 完全同址,免改。INTT 原地。SUB:w = v' − psum,(v'−psum) 负则 +Q。**关键:v'/psum 读口冲突 → D1 把 v' 落到 bank_a slot DEC_VASLOT=1(s_hat 在 j*K,slot 1 恒空 K≥2),SUB 时 psum(bank_t)+v'(bank_a)并行读,正如 V-ADD 并读 psum+e2。** K=2/3/4 w 全过。
-- **D4 — m' = byteEncode₁(Compress₁(w))**:打包器 d=1。dbg 对 m'(== KAT 解密的 m')。
+- **D4 — m' = byteEncode₁(Compress₁(w))** ✅:ST_DEC_MENC,逐系数读 bank_t[UPSUM] 的 w,Compress₁(w)=1 iff 832<w≤2496(Q=3329),LSB-first 打包进 mprime_r[255:0],经 dbg_mprime_o 暴露。TB verify_d4 对 32 字节 golden(== KAT 解密的 m'==原始 m)。K=2/3/4 全过,KG/Enc 回归通过。K-PKE.Decrypt 硬件全链路打通。
-- **D5 — G(m'‖h) → (K',r') + J(z‖c) → K̄**:G 复用、J 多块(0x1F pad)。dbg 对 K'/r'/K̄。
+- **D5 — G(m'‖h) → (K',r') + J(z‖c) → K̄** ✅:G 复用单块 SHA3-512 路径(ST_DEC_G,mode=11,dec_g_data={hek_r,mprime_r}),输出 K'→ss_r(候选 ss,ss_o),r'→r_r(D6 PRF 种子,dbg_r_o)。J 复用多块吸收口(ST_DEC_J,mb_en=1),仿照 H(ek) 机器组装 136B/块,字节源 g<32 取 z_r、32≤g<msglen 取 c_in_bram、否则 SHAKE256 pad(0x1F 后缀,末字节|0x80,与 H 的 0x06 唯一区别)。mb_* 端口按 ST_DEC_J 在 H/J 间多路选择。K̄→kbar_r(dbg_kbar_o)。**踩坑:c_in_bram 读经 cin_rd_addr_r 寄存器 + BRAM 寄存 = 2 拍延迟,而组装/写回流水只容 1 拍 → z→c 边界首个 c 字节(byte32)读到 X,毒化整个 keccak。改为 ST_DEC_J 时 cin_rd_addr 组合直接取 dj_c_idx(去掉寄存器级),数据次拍到达正好对齐写回。** K=2/3/4(密文 768/1088/1568B → 6/9/12 块)全过;K'==KAT ss(有效密文)验证 FO 正确;KG/Enc 回归通过。
-- **D6 — c' = Encrypt(ek_pke,m',r')**:复用 Encaps E1–E7 写 ct_bram。dbg 对 c'==KAT.ct(有效 ct 时)。
+- **D6 — c' = Encrypt(ek_pke,m',r')** ✅:整条 Encaps E1–E7 流水直接复用——ST_DEC_J 完成后跳 ST_ENC_LOAD(rho 从 ek_bram 的 ek_pke 区载入,与 Encaps 同 offset 384k),经 A→C→N→U→C1→TDEC→E2MV→V→C2 跑完写 ct_bram。复用前提全部就位:r'(CBD 种子)在 r_r、ek_pke 在 ek_bram(D0 load 时 dk_ld_ekpke 写入)。**关键改动:D4 把 m' 直接打包进 m_r(而非独立 mprime_r),因为 Encaps V 的 mu=m_r[idx]、dbg_mprime_o 也改指 m_r;省一个寄存器且让重加密天然读到 m'。** ST_ENC_LOAD 的 arming 扩展为从 ST_ENC_G 或 ST_DEC_J 进入皆触发。**注意:重加密覆盖 bank_a/se/t,故 D1–D3 的 bank 检查在 run 末已失效;TB 改为只校验存活的寄存器/BRAM 工件(D0 解析、m'、K'/r'/K̄、c'),bank 阶段正确性由早期分阶段构建 + c' 传递性保证。** K=2/3/4 c'==golden(==有效密文 c)全过,KG/Enc 回归通过。
-- **D7 — 比较 + 拒绝 mux + 端到端 KAT**:c'==c 常量时间比较,ss=mux。干净 TB:
+- **D7 — 比较 + 拒绝 mux + 端到端 KAT** ✅:ST_DEC_CMP 逐字节走遍整个密文(无早退,恒定工作量),ct_bram(c')与 c_in_bram(c)同址并行读,差异 OR 进 cmp_neq;末字节后锁存 dec_reject。ss_o = dec_reject ? kbar_r(K̄) : ss_r(K'),KeyGen/Encaps 因 dec_reject=0 原样透传。ST_ENC_C2 终态按 op_r 分流(Decaps→CMP,Encaps→DONE)。TB 单次载 dk 后跑两遍:
-  - 有效 ct(KAT.ct):ss==KAT.ss(c'==c → K')。
+  - 有效 ct(KAT.ct):ss==KAT.ss(c'==c → K'),reject=0 ✓。
-  - 损坏 ct(KAT ct_n / ss_n):ss==KAT.ss_n(c'≠c → K̄)。
+  - 损坏 ct(KAT ct_n / ss_n):ss==KAT.ss_n(c'≠c → K̄=J(z‖ct_n)),reject=1 ✓。
-  - K=2/3/4 各 count=0..N。
+  - K=2/3/4 各 3 case 全过;KG/Enc 回归通过。**至此 ML-KEM(KeyGen+Encaps+Decaps,含隐式拒绝)硬件全功能打通。**
 
 ## 验证
 - 新 `dump_decaps.rs`(ml-kem-r examples,工作树):出 D1–D6 中间量(u'/v'/s_hat/u_hat/w/m'/K'/K̄)256-coeff / 32B golden。

run_hello.sh

@@ -0,0 +1,25 @@
+#!/usr/bin/env bash
+# run_hello.sh - compile + run an ML-KEM hello_world hardware testbench.
+#   ./run_hello.sh          single-instance protocol (default)
+#   ./run_hello.sh two      two-instance (genenc + dec) protocol
+set -e
+cd "$(dirname "$0")"
+source /opt/Xilinx/Vivado/2019.2/settings64.sh >/dev/null 2>&1
+export LD_PRELOAD="/usr/lib64/libtinfo.so.5"
+rm -rf xsim.dir .Xil
+
+if [ "$1" = "two" ]; then
+    TB=tb_mlkem_two_inst_xsim; SNAP=mlkem_two
+else
+    TB=tb_mlkem_hello_world_xsim; SNAP=mlkem_hello
+fi
+
+# compile the RTL (every non-TB xvlog line from the shared tcl)
+grep -E '^xvlog ' sync_rtl/top/TB/xsim_run.tcl | grep -v 'TB/tb_' | while read -r cmd; do
+    eval "$cmd" >/dev/null
+done
+
+xvlog -sv --relax sync_rtl/top/TB/$TB.v >/dev/null
+xelab $TB -s $SNAP --timescale 1ns/1ps >/dev/null 2>&1
+xsim $SNAP -R 2>/dev/null | grep -vE '^(#|INFO|Time resolution|run -all|exit|xsim|Vivado|====.*Simulator|SW Build|IP Build|Copyright|Tool Version|Start of|source |## )' | sed '/^$/N;/^\n$/D'
+

sync_rtl/top/TB/tb_mlkem_dec_katK_xsim.v

@@ -25,7 +25,7 @@ module tb_mlkem_dec_katK_xsim;
     reg         c_in_we=0;  reg [10:0] c_in_addr=0;  reg [7:0] c_in_byte=0;
     wire [255:0] ss_o;
     reg  [10:0] dbg_ct_idx_i=0; wire [7:0] dbg_ct_o;
-    reg [3:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
+    reg [5:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
     reg dbg_byte_sel_i=0; reg [10:0] dbg_byte_idx_i=0; wire [7:0] dbg_byte_o;
     reg [11:0] dbg_dk_idx_i=0; wire [7:0] dbg_dk_o;
     wire [255:0] dbg_rho_o, dbg_sigma_o, dbg_r_o, dbg_hek_o;
@@ -51,9 +51,11 @@ module tb_mlkem_dec_katK_xsim;
 
     reg [7:0] dk_b [0:DKB-1];
     reg [7:0] ct_b [0:CTB-1];
+    reg [7:0] ctn_b [0:CTB-1];
     reg [7:0] ss_b [0:31];
+    reg [7:0] ssn_b [0:31];
     integer c, i, j, errors, casenum;
-    reg [8*80-1:0] tag, dkfile, ctfile, ssfile;
+    reg [8*80-1:0] tag, dkfile, ctfile, ssfile, ctnfile, ssnfile;
 
     initial begin
         if (!$value$plusargs("CASE=%d", casenum)) casenum = 0;
@@ -61,41 +63,110 @@ module tb_mlkem_dec_katK_xsim;
         $sformat(dkfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_dk.hex", tag, casenum);
         $sformat(ctfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_ct.hex", tag, casenum);
         $sformat(ssfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_ss.hex", tag, casenum);
+        $sformat(ctnfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_ctn.hex", tag, casenum);
+        $sformat(ssnfile, "sync_rtl/top/TB/vectors/dec_%0s_c%0d_ssn.hex", tag, casenum);
         $readmemh(dkfile, dk_b);
         $readmemh(ctfile, ct_b);
         $readmemh(ssfile, ss_b);
+        $readmemh(ctnfile, ctn_b);
+        $readmemh(ssnfile, ssn_b);
         k_i = KP[2:0];
 
         $display("=== ML-KEM K=%0d Decaps KAT case %0d (D0: load+parse) ===", KP, casenum);
 
         rst_n=0; repeat(4) @(posedge clk); rst_n=1; @(posedge clk);
 
-        // ---- stream dk into the design (1 byte/cycle) ----
+        // ---- stream dk into the design (1 byte/cycle); persists for both runs ----
         for (i = 0; i < DKB; i = i + 1) begin
             dk_in_we = 1'b1; dk_in_addr = i[11:0]; dk_in_byte = dk_b[i];
             @(posedge clk);
         end
         dk_in_we = 1'b0;
 
-        // ---- stream ct into c_in_bram (1 byte/cycle) ----
+        errors = 0;
-        for (i = 0; i < CTB; i = i + 1) begin
-            c_in_we = 1'b1; c_in_addr = i[10:0]; c_in_byte = ct_b[i];
-            @(posedge clk);
-        end
-        c_in_we = 1'b0; @(posedge clk);
 
-        // ---- run Decaps ----
+        // ================= Run 1: valid ciphertext (accept path) =================
-        start_i=1; @(posedge clk); start_i=0;
+        // ct == c, so c' == c, no implicit reject: ss == K' == KAT ss.
-        c=0; while(!done_o && c<2000000) begin @(posedge clk); c=c+1; end
+        run_decaps(0);   // 0 = use ct_b
-        if(!done_o) begin $display("FAIL K=%0d case %0d: timeout", KP, casenum); $finish; end
+        verify_d0;        // dk parse (errors NOT reset here; see verify_d0 note)
-        $display("=== Decaps D0 done in %0d cyc ===", c);
+        verify_d4;        // m' (in m_r, survives the re-encrypt)
+        verify_d5;        // K'/r'/K-bar
+        verify_d6;        // c' == golden
+        verify_d7(0);     // ss_o == KAT ss, dec_reject == 0
 
-        verify_d0;
+        // ================= Run 2: corrupted ciphertext (reject path) =============
+        // ct_n != c, so c' != c -> implicit reject: ss == K-bar == J(z||ct_n) == ss_n.
+        run_decaps(1);   // 1 = use ctn_b
+        verify_d7(1);     // ss_o == KAT ss_n, dec_reject == 1
+
+        if (errors == 0) $display("K=%0d CASE %0d PASS (D7): end-to-end Decaps (accept + reject) OK", KP, casenum);
+        else             $display("K=%0d CASE %0d FAIL (D7): %0d total errors", KP, casenum, errors);
         $finish;
     end
 
     initial begin #120000000; $display("FAIL: global timeout"); $finish; end
 
+    // read one stored coefficient at (slot, idx): present addr, wait for the
+    // bank read (sd_bram, 1 cyc) + dbg_coeff_r register (1 cyc) + settle.
+    task rdcoeff;
+        input  [5:0] slot; input [7:0] idx; output [11:0] val;
+        begin
+            dbg_slot_i = slot; dbg_idx_i = idx;
+            @(posedge clk); @(posedge clk); @(posedge clk);
+            val = dbg_coeff_o;
+        end
+    endtask
+
+    // Stream a ciphertext into c_in_bram (sel 0 = valid ct_b, 1 = corrupted ctn_b),
+    // pulse start_i, and wait for done_o. dk is already loaded and persists.
+    task run_decaps;
+        input sel;
+        integer ii;
+        begin
+            for (ii = 0; ii < CTB; ii = ii + 1) begin
+                c_in_we = 1'b1; c_in_addr = ii[10:0];
+                c_in_byte = sel ? ctn_b[ii] : ct_b[ii];
+                @(posedge clk);
+            end
+            c_in_we = 1'b0; @(posedge clk);
+            start_i=1; @(posedge clk); start_i=0;
+            c=0; while(!done_o && c<2000000) begin @(posedge clk); c=c+1; end
+            if(!done_o) begin $display("FAIL K=%0d case %0d: timeout (sel=%0d)", KP, casenum, sel); $finish; end
+            $display("=== Decaps run (sel=%0d) done in %0d cyc ===", sel, c);
+            // settle so dbg taps reflect the finished run
+            repeat(2) @(posedge clk);
+        end
+    endtask
+
+    // D7: end-to-end shared secret. sel=0 (accept): ss_o == KAT ss, dec_reject=0.
+    // sel=1 (reject): ss_o == KAT ss_n (= K-bar = J(z||ct_n)), dec_reject=1.
+    task verify_d7;
+        input sel;
+        integer be;
+        reg [255:0] exp;
+        begin
+            be = 0;
+            for (j = 0; j < 32; j = j + 1)
+                exp[8*j +: 8] = sel ? ssn_b[j] : ss_b[j];
+            for (j = 0; j < 32; j = j + 1)
+                if (ss_o[8*j +: 8] !== exp[8*j +: 8]) begin
+                    if (be < 4) $display("  ss[%0d] got=%02x exp=%02x", j, ss_o[8*j +: 8], exp[8*j +: 8]);
+                    be = be + 1;
+                end
+            if (be == 0)
+                $display("  PASS: ss == KAT %0s (32 bytes), reject=%b",
+                    sel ? "ss_n (reject)" : "ss (accept)", dut.dec_reject);
+            else
+                $display("  FAIL: ss %0d byte mismatches (sel=%0d, reject=%b)", be, sel, dut.dec_reject);
+            errors = errors + be;
+            // also check the reject flag matches the expectation
+            if (dut.dec_reject !== sel) begin
+                $display("  FAIL: dec_reject=%b expected %b", dut.dec_reject, sel);
+                errors = errors + 1;
+            end
+        end
+    endtask
+
     // D0: verify dk parse. H(ek)=dk[768K+32:+32], z=dk[768K+64:+32] captured into
     // hek_r/z_r (dbg_dech_o/dbg_decz_o). ek_pke=dk[384K:768K+32] in ek_bram
     // (dbg_byte sel=0), dk_pke=dk[0:384K] in dkp_bram (sel=1).
@@ -103,12 +174,14 @@ module tb_mlkem_dec_katK_xsim;
         integer be;
         reg [7:0] got;
         begin
-            errors = 0;
+            // errors is initialized by the caller (main flow), not here.
             // H(ek)
+            be = 0;
             for (j = 0; j < 32; j = j + 1)
-                if (dbg_dech_o[8*j +: 8] !== dk_b[DKPB + EKB + j]) errors = errors + 1;
+                if (dbg_dech_o[8*j +: 8] !== dk_b[DKPB + EKB + j]) be = be + 1;
-            if (errors == 0) $display("  PASS: H(ek) parsed == dk[768K+32 ..]");
+            if (be == 0) $display("  PASS: H(ek) parsed == dk[768K+32 ..]");
-            else             $display("  FAIL: H(ek) %0d byte mismatches", errors);
+            else         $display("  FAIL: H(ek) %0d byte mismatches", be);
+            errors = errors + be;
 
             // z
             be = 0;
@@ -145,9 +218,202 @@ module tb_mlkem_dec_katK_xsim;
             if (be == 0) $display("  PASS: dk_pke round-trip (BRAM) == dk[0 ..]");
             else         $display("  FAIL: dk_pke %0d byte mismatches", be);
             errors = errors + be;
+            if (errors == 0) $display("  D0 subcheck PASS: dk parse OK");
+            else             $display("  D0 subcheck FAIL: %0d errors", errors);
+        end
+    endtask
 
-            if (errors == 0) $display("K=%0d CASE %0d PASS (D0): dk parse OK", KP, casenum);
+    // D1: verify u'[i] (bank_se rel i, abs slot K*K+i) and v' (bank_t rel
-            else             $display("K=%0d CASE %0d FAIL (D0): %0d total errors", KP, casenum, errors);
+    // DEC_VSLOT=2, abs slot K*K+2*K+2) against the decode-decompress golden.
+    reg [11:0] up_g [0:255];
+    reg [11:0] vp_g [0:255];
+    task verify_d1;
+        integer i, j, be, ndiff;
+        reg [8*100-1:0] fn;
+        reg [11:0] got;
+        begin
+            ndiff = 0;
+            // u'[i] is NOT checked here: D2's forward NTT transforms u' in place
+            // in bank_se rel 0..K-1, so by the time the run finishes those slots
+            // hold u_hat. u' correctness is proven transitively in verify_d2
+            // (u_hat == NTT(u') golden). Only v' (bank_a slot 1, untouched) checked.
+            // v' lives in bank_a DEC_VASLOT=1 (abs slot 1).
+            $sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_vp.hex", KP, casenum);
+            $readmemh(fn, vp_g);
+            be = 0;
+            for (j = 0; j < 256; j = j + 1) begin
+                rdcoeff(1, j[7:0], got);
+                if (got !== vp_g[j]) begin
+                    if (be < 4) $display("  v'[%0d] got=%03x exp=%03x", j, got, vp_g[j]);
+                    be = be + 1;
+                end
+            end
+            if (be == 0) $display("  PASS: v' == golden (256 coeffs)");
+            else         $display("  FAIL: v' %0d coeff mismatches", be);
+            ndiff = ndiff + be;
+            errors = errors + ndiff;
+        end
+    endtask
+
+    // D2: verify s_hat[i] (bank_a slot i*K, byteDecode12 dk_pke) and
+    // u_hat[i] (bank_se rel slot i, = NTT(u'[i])) against golden.
+    reg [11:0] sh_g [0:255];
+    reg [11:0] uh_g [0:255];
+    task verify_d2;
+        integer i, j, be, ndiff;
+        reg [8*100-1:0] fn;
+        reg [11:0] got;
+        begin
+            ndiff = 0;
+            for (i = 0; i < KP; i = i + 1) begin
+                // s_hat[i] at bank_a slot i*KP
+                $sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_shat_%0d.hex", KP, casenum, i);
+                $readmemh(fn, sh_g);
+                be = 0;
+                for (j = 0; j < 256; j = j + 1) begin
+                    rdcoeff(i*KP, j[7:0], got);
+                    if (got !== sh_g[j]) begin
+                        if (be < 4) $display("  s_hat[%0d][%0d] got=%03x exp=%03x", i, j, got, sh_g[j]);
+                        be = be + 1;
+                    end
+                end
+                if (be == 0) $display("  PASS: s_hat[%0d] == golden", i);
+                else         $display("  FAIL: s_hat[%0d] %0d mismatches", i, be);
+                ndiff = ndiff + be;
+                // u_hat[i] at bank_se rel slot i (abs KP*KP + i)
+                $sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_uhat_%0d.hex", KP, casenum, i);
+                $readmemh(fn, uh_g);
+                be = 0;
+                for (j = 0; j < 256; j = j + 1) begin
+                    rdcoeff(KP*KP + i, j[7:0], got);
+                    if (got !== uh_g[j]) begin
+                        if (be < 4) $display("  u_hat[%0d][%0d] got=%03x exp=%03x", i, j, got, uh_g[j]);
+                        be = be + 1;
+                    end
+                end
+                if (be == 0) $display("  PASS: u_hat[%0d] == golden", i);
+                else         $display("  FAIL: u_hat[%0d] %0d mismatches", i, be);
+                ndiff = ndiff + be;
+            end
+            errors = errors + ndiff;
+        end
+    endtask
+
+    // D3: verify w (bank_t rel UPSUM=1, abs slot K*K+2*K+1) == golden.
+    reg [11:0] w_g [0:255];
+    task verify_d3;
+        integer j, be;
+        reg [8*100-1:0] fn;
+        reg [11:0] got;
+        begin
+            $sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_w.hex", KP, casenum);
+            $readmemh(fn, w_g);
+            be = 0;
+            for (j = 0; j < 256; j = j + 1) begin
+                rdcoeff(KP*KP + 2*KP + 1, j[7:0], got);
+                if (got !== w_g[j]) begin
+                    if (be < 4) $display("  w[%0d] got=%03x exp=%03x", j, got, w_g[j]);
+                    be = be + 1;
+                end
+            end
+            if (be == 0) $display("  PASS: w == golden (256 coeffs)");
+            else         $display("  FAIL: w %0d coeff mismatches", be);
+            errors = errors + be;
+        end
+    endtask
+
+    // D4: verify m' = byteEncode_1(Compress_1(w)) == golden (32 bytes via dbg).
+    reg [7:0] mp_g [0:31];
+    task verify_d4;
+        integer j, be;
+        reg [8*100-1:0] fn;
+        begin
+            $sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_mprime.hex", KP, casenum);
+            $readmemh(fn, mp_g);
+            be = 0;
+            for (j = 0; j < 32; j = j + 1) begin
+                if (dbg_mprime_o[8*j +: 8] !== mp_g[j]) begin
+                    if (be < 4) $display("  m'[%0d] got=%02x exp=%02x", j, dbg_mprime_o[8*j +: 8], mp_g[j]);
+                    be = be + 1;
+                end
+            end
+            if (be == 0) $display("  PASS: m' == golden (32 bytes)");
+            else         $display("  FAIL: m' %0d byte mismatches", be);
+            errors = errors + be;
+        end
+    endtask
+
+    // D5: verify K' (ss_o), r' (dbg_r_o), K-bar (dbg_kbar_o) against golden.
+    reg [7:0] kp_b [0:31];
+    reg [7:0] rp_b [0:31];
+    reg [7:0] kb_b [0:31];
+    task verify_d5;
+        integer j, be;
+        reg [8*100-1:0] fn;
+        begin
+            // K' = G(m'||h) low half -> ss_o
+            $sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_kprime.hex", KP, casenum);
+            $readmemh(fn, kp_b);
+            be = 0;
+            for (j = 0; j < 32; j = j + 1)
+                if (ss_o[8*j +: 8] !== kp_b[j]) begin
+                    if (be < 4) $display("  K'[%0d] got=%02x exp=%02x", j, ss_o[8*j +: 8], kp_b[j]);
+                    be = be + 1;
+                end
+            if (be == 0) $display("  PASS: K' == golden (32 bytes)");
+            else         $display("  FAIL: K' %0d byte mismatches", be);
+            errors = errors + be;
+            // r' = G(m'||h) high half -> dbg_r_o
+            $sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_rprime.hex", KP, casenum);
+            $readmemh(fn, rp_b);
+            be = 0;
+            for (j = 0; j < 32; j = j + 1)
+                if (dbg_r_o[8*j +: 8] !== rp_b[j]) begin
+                    if (be < 4) $display("  r'[%0d] got=%02x exp=%02x", j, dbg_r_o[8*j +: 8], rp_b[j]);
+                    be = be + 1;
+                end
+            if (be == 0) $display("  PASS: r' == golden (32 bytes)");
+            else         $display("  FAIL: r' %0d byte mismatches", be);
+            errors = errors + be;
+            // K-bar = J(z||c) -> dbg_kbar_o
+            $sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_kbar.hex", KP, casenum);
+            $readmemh(fn, kb_b);
+            be = 0;
+            for (j = 0; j < 32; j = j + 1)
+                if (dbg_kbar_o[8*j +: 8] !== kb_b[j]) begin
+                    if (be < 4) $display("  K-bar[%0d] got=%02x exp=%02x", j, dbg_kbar_o[8*j +: 8], kb_b[j]);
+                    be = be + 1;
+                end
+            if (be == 0) $display("  PASS: K-bar == golden (32 bytes)");
+            else         $display("  FAIL: K-bar %0d byte mismatches", be);
+            errors = errors + be;
+        end
+    endtask
+
+    // D6: verify c' = K-PKE.Encrypt(ek_pke, m', r') in ct_bram == golden.
+    // ct length = 32*(du*K + dv): K2=768, K3=1088, K4=1568.
+    reg [7:0] cp_b [0:1567];
+    task verify_d6;
+        integer i, be, ctlen;
+        reg [8*100-1:0] fn;
+        reg [7:0] got;
+        begin
+            ctlen = (KP == 2) ? 768 : (KP == 3) ? 1088 : 1568;
+            $sformat(fn, "sync_rtl/top/TB/vectors/decgold/dc_k%0d_c%0d_cprime.hex", KP, casenum);
+            $readmemh(fn, cp_b);
+            be = 0;
+            for (i = 0; i < ctlen; i = i + 1) begin
+                dbg_ct_idx_i = i[10:0];
+                @(posedge clk); @(posedge clk); @(posedge clk);
+                got = dbg_ct_o;
+                if (got !== cp_b[i]) begin
+                    if (be < 6) $display("  c'[%0d] got=%02x exp=%02x", i, got, cp_b[i]);
+                    be = be + 1;
+                end
+            end
+            if (be == 0) $display("  PASS: c' == golden (%0d bytes)", ctlen);
+            else         $display("  FAIL: c' %0d byte mismatches", be);
+            errors = errors + be;
         end
     endtask
 endmodule

sync_rtl/top/TB/tb_mlkem_hello_world_xsim.v

@@ -0,0 +1,199 @@
+// tb_mlkem_hello_world_xsim.v - Hardware run of ml-kem-r examples/hello_world.rs.
+//
+// Mirrors the Rust example end-to-end on the mlkem_top DUT (ML-KEM-512, K=2):
+//   1. Alice: KeyGen(d=0x42..., z=0x77...)            -> (ek 800B, dk 1632B)
+//   2. Bob:   Encaps(ek, m=0xDE...)                   -> (shared_key, kem_ct 768B)
+//   3. Bob:   XOR-encrypt "hello world" with key      -> encrypted
+//   4. Alice: Decaps(dk, kem_ct)                       -> recovered_key
+//   5. Alice: XOR-decrypt encrypted with key          -> "hello world"
+//   6. Verify: shared_key == recovered_key, decrypted == message
+//
+// The whole protocol runs on ONE DUT instance: ek/dk are read out of KeyGen via
+// the dbg taps, then fed back into Encaps/Decaps via the streaming input ports,
+// exactly as a real ek/dk/ct would cross the wire between Alice and Bob.
+//
+// Each step prints its inputs and outputs.
+//
+//   xelab tb_mlkem_hello_world_xsim ; xsim
+`timescale 1ns/1ps
+module tb_mlkem_hello_world_xsim;
+    localparam KP   = 2;                 // ML-KEM-512
+    localparam EKB  = 384*KP + 32;       // 800
+    localparam DKB  = 768*KP + 96;       // 1632
+    localparam CTB  = 32*(10*KP + 4);    // 768
+    localparam MLEN = 11;                // "hello world"
+
+    reg clk=0, rst_n=0, start_i=0;
+    reg [2:0]   k_i = KP;
+    reg [1:0]   op_i = 0;
+    reg [255:0] d_i=0, z_i=0, msg_i=0;
+    wire busy_o, done_o;
+    reg         ek_in_we=0; reg [10:0] ek_in_addr=0; reg [7:0] ek_in_byte=0;
+    reg         dk_in_we=0; reg [11:0] dk_in_addr=0; reg [7:0] dk_in_byte=0;
+    reg         c_in_we=0;  reg [10:0] c_in_addr=0;  reg [7:0] c_in_byte=0;
+    wire [255:0] ss_o;
+    reg  [10:0] dbg_ct_idx_i=0; wire [7:0] dbg_ct_o;
+    reg [5:0] dbg_slot_i=0; reg [7:0] dbg_idx_i=0; wire [11:0] dbg_coeff_o;
+    reg dbg_byte_sel_i=0; reg [10:0] dbg_byte_idx_i=0; wire [7:0] dbg_byte_o;
+    reg [11:0] dbg_dk_idx_i=0; wire [7:0] dbg_dk_o;
+    wire [255:0] dbg_rho_o, dbg_sigma_o, dbg_r_o, dbg_hek_o;
+    wire [255:0] dbg_mprime_o, dbg_kbar_o, dbg_decz_o, dbg_dech_o;
+
+    mlkem_top dut (
+        .clk(clk), .rst_n(rst_n), .k_i(k_i), .op_i(op_i),
+        .d_i(d_i), .z_i(z_i), .msg_i(msg_i), .start_i(start_i),
+        .busy_o(busy_o), .done_o(done_o),
+        .ek_in_we(ek_in_we), .ek_in_addr(ek_in_addr), .ek_in_byte(ek_in_byte),
+        .dk_in_we(dk_in_we), .dk_in_addr(dk_in_addr), .dk_in_byte(dk_in_byte),
+        .c_in_we(c_in_we), .c_in_addr(c_in_addr), .c_in_byte(c_in_byte),
+        .ss_o(ss_o), .dbg_ct_idx_i(dbg_ct_idx_i), .dbg_ct_o(dbg_ct_o),
+        .dbg_slot_i(dbg_slot_i), .dbg_idx_i(dbg_idx_i), .dbg_coeff_o(dbg_coeff_o),
+        .dbg_byte_sel_i(dbg_byte_sel_i), .dbg_byte_idx_i(dbg_byte_idx_i), .dbg_byte_o(dbg_byte_o),
+        .dbg_dk_idx_i(dbg_dk_idx_i), .dbg_dk_o(dbg_dk_o),
+        .dbg_rho_o(dbg_rho_o), .dbg_sigma_o(dbg_sigma_o),
+        .dbg_r_o(dbg_r_o), .dbg_hek_o(dbg_hek_o),
+        .dbg_mprime_o(dbg_mprime_o), .dbg_kbar_o(dbg_kbar_o),
+        .dbg_decz_o(dbg_decz_o), .dbg_dech_o(dbg_dech_o)
+    );
+    always #5 clk = ~clk;
+
+    // storage shuttled between operations (the "wire" between Alice and Bob)
+    reg [7:0] ek_b  [0:EKB-1];
+    reg [7:0] dk_b  [0:DKB-1];
+    reg [7:0] ct_b  [0:CTB-1];
+    reg [7:0] msg_b [0:MLEN-1];          // "hello world"
+    reg [7:0] enc_b [0:MLEN-1];          // XOR-encrypted
+    reg [7:0] dec_b [0:MLEN-1];          // XOR-decrypted
+    reg [255:0] shared_key, recovered_key;
+    integer c, i, j, errors;
+
+    // ---- pulse start and wait for done ----
+    task run_op;
+        input [1:0] op;
+        begin
+            op_i = op;
+            start_i = 1'b1; @(posedge clk); start_i = 1'b0;
+            c = 0;
+            while (!done_o && c < 4000000) begin @(posedge clk); c = c + 1; end
+            if (!done_o) begin $display("FAIL: op=%0d timeout", op); $finish; end
+        end
+    endtask
+
+    task print_hex32;        // print a 256-bit value as 32 hex bytes, byte 0 first
+        input [255:0] v;
+        begin
+            for (j = 0; j < 32; j = j + 1) $write("%02x", v[8*j +: 8]);
+            $write("\n");
+        end
+    endtask
+
+    initial begin
+        errors = 0;
+        // message bytes "hello world"
+        msg_b[0]="h"; msg_b[1]="e"; msg_b[2]="l"; msg_b[3]="l"; msg_b[4]="o";
+        msg_b[5]=" "; msg_b[6]="w"; msg_b[7]="o"; msg_b[8]="r"; msg_b[9]="l"; msg_b[10]="d";
+
+        $display("=== ML-KEM hello_world (hardware, ML-KEM-512) ===");
+        $write("Original: \"");
+        for (i = 0; i < MLEN; i = i + 1) $write("%c", msg_b[i]);
+        $display("\"\n");
+
+        rst_n=0; repeat(4) @(posedge clk); rst_n=1; @(posedge clk);
+
+        // ===== Step 1: Alice — KeyGen(d, z) =====
+        d_i = {32{8'h42}};     // d = 0x42 repeated (byte 0 in d_i[7:0])
+        z_i = {32{8'h77}};     // z = 0x77 repeated
+        $display("[1] Alice KeyGen");
+        $write("    in  d = "); print_hex32(d_i);
+        $write("    in  z = "); print_hex32(z_i);
+        run_op(2'd0);
+        // read ek (sel=0) out of ek_bram
+        dbg_byte_sel_i = 1'b0;
+        for (i = 0; i < EKB; i = i + 1) begin
+            dbg_byte_idx_i = i[10:0]; @(posedge clk); @(posedge clk);
+            ek_b[i] = dbg_byte_o;
+        end
+        // read full dk (1632 B) via dbg_dk
+        for (i = 0; i < DKB; i = i + 1) begin
+            dbg_dk_idx_i = i[11:0]; @(posedge clk); @(posedge clk);
+            dk_b[i] = dbg_dk_o;
+        end
+        $display("    out ek = %0d B (ek[0:8] = %02x %02x %02x %02x %02x %02x %02x %02x ...)",
+                 EKB, ek_b[0],ek_b[1],ek_b[2],ek_b[3],ek_b[4],ek_b[5],ek_b[6],ek_b[7]);
+        $display("    out dk = %0d B (dk[0:8] = %02x %02x %02x %02x %02x %02x %02x %02x ...)",
+                 DKB, dk_b[0],dk_b[1],dk_b[2],dk_b[3],dk_b[4],dk_b[5],dk_b[6],dk_b[7]);
+        $display("    (cycles: %0d)\n", c);
+
+        // ===== Step 2: Bob — Encaps(ek, m) =====
+        // stream ek back into ek_bram (Bob receives Alice's public key)
+        for (i = 0; i < EKB; i = i + 1) begin
+            ek_in_we = 1'b1; ek_in_addr = i[10:0]; ek_in_byte = ek_b[i];
+            @(posedge clk);
+        end
+        ek_in_we = 1'b0; @(posedge clk);
+        msg_i = {32{8'hDE}};   // m = 0xDE repeated
+        $display("[2] Bob Encaps");
+        $write("    in  ek = %0d B;  in m = ", EKB); print_hex32(msg_i);
+        run_op(2'd1);
+        shared_key = ss_o;
+        // read ct (768 B) out of ct_bram
+        for (i = 0; i < CTB; i = i + 1) begin
+            dbg_ct_idx_i = i[10:0]; @(posedge clk); @(posedge clk);
+            ct_b[i] = dbg_ct_o;
+        end
+        $write("    out shared_key = "); print_hex32(shared_key);
+        $display("    out kem_ct = %0d B (ct[0:8] = %02x %02x %02x %02x %02x %02x %02x %02x ...)",
+                 CTB, ct_b[0],ct_b[1],ct_b[2],ct_b[3],ct_b[4],ct_b[5],ct_b[6],ct_b[7]);
+        $display("    (cycles: %0d)\n", c);
+
+        // ===== Step 3: Bob — XOR-encrypt "hello world" with shared_key =====
+        for (i = 0; i < MLEN; i = i + 1)
+            enc_b[i] = msg_b[i] ^ shared_key[8*(i % 32) +: 8];
+        $display("[3] Bob encrypt (XOR stream, demo)");
+        $write("    in  msg       = "); for (i=0;i<MLEN;i=i+1) $write("%02x ", msg_b[i]); $write("\n");
+        $write("    out encrypted = "); for (i=0;i<MLEN;i=i+1) $write("%02x ", enc_b[i]); $write("\n\n");
+
+        // ===== Step 4: Alice — Decaps(dk, kem_ct) =====
+        for (i = 0; i < DKB; i = i + 1) begin
+            dk_in_we = 1'b1; dk_in_addr = i[11:0]; dk_in_byte = dk_b[i];
+            @(posedge clk);
+        end
+        dk_in_we = 1'b0;
+        for (i = 0; i < CTB; i = i + 1) begin
+            c_in_we = 1'b1; c_in_addr = i[10:0]; c_in_byte = ct_b[i];
+            @(posedge clk);
+        end
+        c_in_we = 1'b0; @(posedge clk);
+        $display("[4] Alice Decaps");
+        $display("    in  dk = %0d B;  in kem_ct = %0d B", DKB, CTB);
+        run_op(2'd2);
+        recovered_key = ss_o;
+        $write("    out recovered_key = "); print_hex32(recovered_key);
+        $display("    (cycles: %0d)\n", c);
+
+        // ===== Step 5: Alice — XOR-decrypt =====
+        for (i = 0; i < MLEN; i = i + 1)
+            dec_b[i] = enc_b[i] ^ recovered_key[8*(i % 32) +: 8];
+        $display("[5] Alice decrypt");
+        $write("    in  encrypted = "); for (i=0;i<MLEN;i=i+1) $write("%02x ", enc_b[i]); $write("\n");
+        $write("    out decrypted = \"");
+        for (i = 0; i < MLEN; i = i + 1) $write("%c", dec_b[i]);
+        $display("\"\n");
+
+        // ===== Step 6: Verify =====
+        if (shared_key !== recovered_key) begin
+            $display("FAIL: shared_key != recovered_key");
+            errors = errors + 1;
+        end
+        for (i = 0; i < MLEN; i = i + 1)
+            if (dec_b[i] !== msg_b[i]) errors = errors + 1;
+
+        if (errors == 0)
+            $display("Success: keys match, message recovered. (hardware ML-KEM-512)");
+        else
+            $display("FAILURE: %0d mismatches", errors);
+        $finish;
+    end
+
+    initial begin #200000000; $display("FAIL: global timeout"); $finish; end
+endmodule

sync_rtl/top/TB/tb_mlkem_two_inst_xsim.v

@@ -0,0 +1,169 @@
+// tb_mlkem_two_inst_xsim.v - ML-KEM hello_world on TWO mlkem_top instances.
+//
+// Models the real two-party split:
+//   * Instance A (u_genenc): Alice/Bob side that does KeyGen THEN Encaps.
+//       - KeyGen(d,z) writes ek into A's own ek_bram and produces dk.
+//       - Encaps(m) reuses that same ek_bram (no re-streaming) -> shared_key, ct.
+//   * Instance B (u_dec):    Alice side that does Decaps.
+//       - receives dk (read out of A via dbg_dk) and ct (read out of A via
+//         dbg_ct), streamed into B's input ports -> recovered_key.
+//
+// Then XOR-encrypt/decrypt "hello world" and verify both keys + message match.
+// Each step prints its inputs and outputs.
+//
+//   xelab tb_mlkem_two_inst_xsim ; xsim
+`timescale 1ns/1ps
+module tb_mlkem_two_inst_xsim;
+    localparam KP   = 2;                 // ML-KEM-512
+    localparam EKB  = 384*KP + 32;       // 800
+    localparam DKB  = 768*KP + 96;       // 1632
+    localparam CTB  = 32*(10*KP + 4);    // 768
+    localparam MLEN = 11;                // "hello world"
+
+    reg clk=0;
+    always #5 clk = ~clk;
+
+    // ---------------- Instance A: KeyGen + Encaps ----------------
+    reg         a_rst_n=0, a_start=0;
+    reg [1:0]   a_op=0;
+    reg [255:0] a_d=0, a_z=0, a_msg=0;
+    wire        a_busy, a_done;
+    wire [255:0] a_ss;
+    reg  [10:0] a_ct_idx=0;  wire [7:0] a_ct_o;
+    reg         a_byte_sel=0; reg [10:0] a_byte_idx=0; wire [7:0] a_byte_o;
+    reg  [11:0] a_dk_idx=0;   wire [7:0] a_dk_o;
+    wire [255:0] a_rho,a_sigma,a_r,a_hek,a_mp,a_kbar,a_dz,a_dh;
+
+    mlkem_top u_genenc (
+        .clk(clk), .rst_n(a_rst_n), .k_i(KP[2:0]), .op_i(a_op),
+        .d_i(a_d), .z_i(a_z), .msg_i(a_msg), .start_i(a_start),
+        .busy_o(a_busy), .done_o(a_done),
+        .ek_in_we(1'b0), .ek_in_addr(11'd0), .ek_in_byte(8'd0),
+        .dk_in_we(1'b0), .dk_in_addr(12'd0), .dk_in_byte(8'd0),
+        .c_in_we(1'b0), .c_in_addr(11'd0), .c_in_byte(8'd0),
+        .ss_o(a_ss), .dbg_ct_idx_i(a_ct_idx), .dbg_ct_o(a_ct_o),
+        .dbg_slot_i(6'd0), .dbg_idx_i(8'd0), .dbg_coeff_o(),
+        .dbg_byte_sel_i(a_byte_sel), .dbg_byte_idx_i(a_byte_idx), .dbg_byte_o(a_byte_o),
+        .dbg_dk_idx_i(a_dk_idx), .dbg_dk_o(a_dk_o),
+        .dbg_rho_o(a_rho), .dbg_sigma_o(a_sigma), .dbg_r_o(a_r), .dbg_hek_o(a_hek),
+        .dbg_mprime_o(a_mp), .dbg_kbar_o(a_kbar), .dbg_decz_o(a_dz), .dbg_dech_o(a_dh)
+    );
+
+    // ---------------- Instance B: Decaps ----------------
+    reg         b_rst_n=0, b_start=0;
+    wire        b_busy, b_done;
+    wire [255:0] b_ss;
+    reg         b_dk_we=0; reg [11:0] b_dk_addr=0; reg [7:0] b_dk_byte=0;
+    reg         b_c_we=0;  reg [10:0] b_c_addr=0;  reg [7:0] b_c_byte=0;
+    wire [255:0] b_rho,b_sigma,b_r,b_hek,b_mp,b_kbar,b_dz,b_dh;
+    wire [7:0]  b_byte_o, b_dk_o, b_ct_o;
+
+    mlkem_top u_dec (
+        .clk(clk), .rst_n(b_rst_n), .k_i(KP[2:0]), .op_i(2'd2),
+        .d_i(256'd0), .z_i(256'd0), .msg_i(256'd0), .start_i(b_start),
+        .busy_o(b_busy), .done_o(b_done),
+        .ek_in_we(1'b0), .ek_in_addr(11'd0), .ek_in_byte(8'd0),
+        .dk_in_we(b_dk_we), .dk_in_addr(b_dk_addr), .dk_in_byte(b_dk_byte),
+        .c_in_we(b_c_we), .c_in_addr(b_c_addr), .c_in_byte(b_c_byte),
+        .ss_o(b_ss), .dbg_ct_idx_i(11'd0), .dbg_ct_o(b_ct_o),
+        .dbg_slot_i(6'd0), .dbg_idx_i(8'd0), .dbg_coeff_o(),
+        .dbg_byte_sel_i(1'b0), .dbg_byte_idx_i(11'd0), .dbg_byte_o(b_byte_o),
+        .dbg_dk_idx_i(12'd0), .dbg_dk_o(b_dk_o),
+        .dbg_rho_o(b_rho), .dbg_sigma_o(b_sigma), .dbg_r_o(b_r), .dbg_hek_o(b_hek),
+        .dbg_mprime_o(b_mp), .dbg_kbar_o(b_kbar), .dbg_decz_o(b_dz), .dbg_dech_o(b_dh)
+    );
+
+    // shuttle storage (the wire between the two instances)
+    reg [7:0] dk_b  [0:DKB-1];
+    reg [7:0] ct_b  [0:CTB-1];
+    reg [7:0] msg_b [0:MLEN-1];
+    reg [7:0] enc_b [0:MLEN-1];
+    reg [7:0] dec_b [0:MLEN-1];
+    reg [255:0] shared_key, recovered_key;
+    integer c, i, j, errors;
+
+    task wait_a; begin
+        c=0; while(!a_done && c<4000000) begin @(posedge clk); c=c+1; end
+        if(!a_done) begin $display("FAIL: instance A timeout (op=%0d)", a_op); $finish; end
+    end endtask
+    task wait_b; begin
+        c=0; while(!b_done && c<4000000) begin @(posedge clk); c=c+1; end
+        if(!b_done) begin $display("FAIL: instance B timeout"); $finish; end
+    end endtask
+
+    task print_hex32; input [255:0] v; begin
+        for (j=0;j<32;j=j+1) $write("%02x", v[8*j +: 8]); $write("\n");
+    end endtask
+
+    initial begin
+        errors = 0;
+        msg_b[0]="h"; msg_b[1]="e"; msg_b[2]="l"; msg_b[3]="l"; msg_b[4]="o";
+        msg_b[5]=" "; msg_b[6]="w"; msg_b[7]="o"; msg_b[8]="r"; msg_b[9]="l"; msg_b[10]="d";
+
+        $display("=== ML-KEM hello_world (TWO instances: genenc + dec, ML-KEM-512) ===");
+        $write("Original: \""); for(i=0;i<MLEN;i=i+1) $write("%c", msg_b[i]); $display("\"\n");
+
+        a_rst_n=0; b_rst_n=0; repeat(4) @(posedge clk); a_rst_n=1; b_rst_n=1; @(posedge clk);
+
+        // ===== Step 1: Instance A — KeyGen(d, z) =====
+        a_d = {32{8'h42}}; a_z = {32{8'h77}};
+        $display("[A.1] KeyGen");
+        $write("      in  d = "); print_hex32(a_d);
+        $write("      in  z = "); print_hex32(a_z);
+        a_op=2'd0; a_start=1; @(posedge clk); a_start=0; wait_a;
+        // read dk out of A (to hand to instance B)
+        for (i=0;i<DKB;i=i+1) begin a_dk_idx=i[11:0]; @(posedge clk); @(posedge clk); dk_b[i]=a_dk_o; end
+        $display("      out ek = %0d B (stays in A's ek_bram); dk = %0d B (dk[0:8]=%02x %02x %02x %02x %02x %02x %02x %02x ...)",
+                 EKB, DKB, dk_b[0],dk_b[1],dk_b[2],dk_b[3],dk_b[4],dk_b[5],dk_b[6],dk_b[7]);
+        $display("      (cycles: %0d)\n", c);
+
+        // ===== Step 2: Instance A — Encaps(ek, m) =====
+        // ek already lives in A's ek_bram from KeyGen; no re-streaming needed.
+        a_msg = {32{8'hDE}};
+        $display("[A.2] Encaps (reuses ek_bram from KeyGen)");
+        $write("      in  m = "); print_hex32(a_msg);
+        a_op=2'd1; a_start=1; @(posedge clk); a_start=0; wait_a;
+        shared_key = a_ss;
+        for (i=0;i<CTB;i=i+1) begin a_ct_idx=i[10:0]; @(posedge clk); @(posedge clk); ct_b[i]=a_ct_o; end
+        $write("      out shared_key = "); print_hex32(shared_key);
+        $display("      out kem_ct = %0d B (ct[0:8]=%02x %02x %02x %02x %02x %02x %02x %02x ...)",
+                 CTB, ct_b[0],ct_b[1],ct_b[2],ct_b[3],ct_b[4],ct_b[5],ct_b[6],ct_b[7]);
+        $display("      (cycles: %0d)\n", c);
+
+        // ===== Step 3: Bob — XOR-encrypt =====
+        for (i=0;i<MLEN;i=i+1) enc_b[i] = msg_b[i] ^ shared_key[8*(i%32) +: 8];
+        $display("[3] encrypt \"hello world\" (XOR stream, demo)");
+        $write("    out encrypted = "); for(i=0;i<MLEN;i=i+1) $write("%02x ", enc_b[i]); $write("\n\n");
+
+        // ===== Step 4: Instance B — Decaps(dk, kem_ct) =====
+        // hand dk + ct from A to B over the streaming input ports
+        for (i=0;i<DKB;i=i+1) begin b_dk_we=1; b_dk_addr=i[11:0]; b_dk_byte=dk_b[i]; @(posedge clk); end
+        b_dk_we=0;
+        for (i=0;i<CTB;i=i+1) begin b_c_we=1; b_c_addr=i[10:0]; b_c_byte=ct_b[i]; @(posedge clk); end
+        b_c_we=0; @(posedge clk);
+        $display("[B.1] Decaps (separate instance)");
+        $display("      in  dk = %0d B, kem_ct = %0d B  (received from instance A)", DKB, CTB);
+        b_start=1; @(posedge clk); b_start=0; wait_b;
+        recovered_key = b_ss;
+        $write("      out recovered_key = "); print_hex32(recovered_key);
+        $display("      (cycles: %0d)\n", c);
+
+        // ===== Step 5: Alice — XOR-decrypt =====
+        for (i=0;i<MLEN;i=i+1) dec_b[i] = enc_b[i] ^ recovered_key[8*(i%32) +: 8];
+        $write("[5] decrypt -> \""); for(i=0;i<MLEN;i=i+1) $write("%c", dec_b[i]); $display("\"\n");
+
+        // ===== Step 6: Verify =====
+        if (shared_key !== recovered_key) begin
+            $display("FAIL: shared_key (A) != recovered_key (B)"); errors=errors+1;
+        end
+        for (i=0;i<MLEN;i=i+1) if (dec_b[i] !== msg_b[i]) errors=errors+1;
+
+        if (errors==0)
+            $display("Success: A.shared_key == B.recovered_key, message recovered across two instances.");
+        else
+            $display("FAILURE: %0d mismatches", errors);
+        $finish;
+    end
+
+    initial begin #400000000; $display("FAIL: global timeout"); $finish; end
+endmodule

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sync_rtl/top/TB/vectors/decgold/dc_k2_c0_kbar.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c0_kprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c0_mprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c0_rprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c0_shat_0.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c0_w.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c1_cprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c1_kbar.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c1_kprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c1_mprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c1_rprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c1_shat_0.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c1_shat_1.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_cprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_kbar.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_kprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_mprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_rprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_shat_0.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_shat_1.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_uhat_0.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_uhat_1.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_up_0.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_up_1.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_vp.hex

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sync_rtl/top/TB/vectors/decgold/dc_k2_c2_w.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_kbar.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_kprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_mprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_rprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_shat_0.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_uhat_1.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_uhat_2.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_up_1.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_up_2.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_vp.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c0_w.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c1_kbar.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c1_kprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c1_mprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c1_rprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c1_shat_0.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c1_shat_1.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c1_up_2.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c1_vp.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c1_w.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c2_kbar.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c2_kprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c2_mprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c2_rprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c2_shat_0.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c2_shat_1.hex

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sync_rtl/top/TB/vectors/decgold/dc_k3_c2_shat_2.hex

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sync_rtl/top/TB/vectors/decgold/dc_k4_c0_kbar.hex

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sync_rtl/top/TB/vectors/decgold/dc_k4_c0_kprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k4_c0_mprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k4_c0_rprime.hex

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sync_rtl/top/TB/vectors/decgold/dc_k4_c0_shat_1.hex

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