2 Commits

Author	SHA1	Message	Date
FallenSigh	4997657d7e	test(comp_decomp): add ML-KEM-1024 d=11/d=5 compress/decompress cases ... Adds 4 Verilator cases covering d_u=11 and d_v=5 (ML-KEM-1024), which the RTL already supports (d is 5-bit, products fit 24 bits). comp_decomp now 120/120 vectors. Also ignore .omo/ session runtime cache and archive the 06-27-sha3-g-test-specific-input trellis task. Verified all 10 modules pass both frameworks: - Verilator: 4334/4334 vectors - XSIM (Vivado 2019.2): all 11 testbenches green, separate committed vectors Oracles independently cross-checked vs hashlib (G/H/J/PRF) and FIPS 203 Alg 7/8/9/10/12 (sample_ntt, sample_cbd, ntt, poly_mul).	2026-06-27 21:04:57 +08:00
FallenSigh	a369a421b7	feat(phase3): implement storage BRAMs and Compress/Decompress ... Phase 3.1 + 3.3: - sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM) - s_bram.v: single-port RAM (rd_en/wr_en, write priority) - comp_decomp_sync.v: streaming compress/decompress with round-half-up Verified: storage 5/5, comp_decomp 60/60 all PASS	2026-06-24 23:28:06 +08:00