2 Commits

Author	SHA1	Message	Date
FallenSigh	d4c3fc86fc	feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules ... Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script	2026-06-25 20:48:38 +08:00
FallenSigh	ae5f0ca048	feat(sha3_chain): add simple SHA3_G integration test ... Phase 3.2: Verifies module chaining works. - sha3_chain_top.v: 3-state FSM (IDLE→BUSY→DONE), feeds d_in→sha3_top(G) - Captures rho[255:0] and sigma[511:256] from SHA3-512 output - Verified: 3/3 bit-exact vs Python G(d||k=2) reference KG full-path FSM (~11 module chain) deferred — too complex for single dispatch.	2026-06-25 00:22:08 +08:00