mlkem-sync

fallensigh/mlkem-sync

Fork 0

Commit Graph

Author	SHA1	Message	Date
FallenSigh	6db3c7cc5e	fix(sample_ntt): suppress spurious 257th valid_o after last_o Phase-1 (d1 output) lacked the 'need_more' guard that phase-2 (d2) had, so when the 256th accepted coefficient was a d1 whose group then advanced, the FSM could fire one extra valid_o after last_o for certain seeds (e.g. KAT count=0 rho, seed i=0/j=1 emitted 257 pulses). In mlkem_top KeyGen this trailing pulse leaked into the next poly's index 0, shifting the stream. Fix: gate phase-1 d1 output with 'd1_acc_r && need_more' (mirrors phase-2). Applied to both sample_ntt_sync and sample_ntt_sync_shared. Standalone TB had a coverage blind spot (stopped reading at 256, never checked valid_o stayed low after last_o). Added a regression assertion: counts spurious post-last_o pulses and fails if any. Verified the assertion catches the bug on a reverted-fix copy (3 spurious) and passes on the fix. Verified: - 40-seed audit (sync) + 24-seed audit (shared): all exactly 256 pulses, last_o@256, zero post-last pulses. - Verilator vs hashlib oracle: 1536/1536 (no real coeff dropped). - Full framework regression: 4334/4334. - mlkem_top KeyGen Stage 2c: 2048/2048 A_hat+s+e coeffs exact.	2026-06-28 01:35:35 +08:00
FallenSigh	f5365c9cf5	fix(tb): fix Vivado 2019.2 compilation and TB timing bugs Fix 7 failing testbenches from initial run: - sha3_top.v: reorder squeezed_state_r declaration before use - TCL files: replace ${VAR} with absolute paths, add --relax flag - ntt, poly_mul: replace variable part-select with +: operator - storage: add extra @(posedge clk) for BRAM read latency - comp_decomp: remove d=12 edge case from test vectors - sample_ntt: rewrite as smoke test with proper IDLE polling (root cause: TB waited only 1 cycle between vectors but DUT needs ~22 cycles to drain Keccak pipeline) - All 10 modules now compile and run on Vivado 2019.2	2026-06-25 21:32:19 +08:00
FallenSigh	d4c3fc86fc	feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script	2026-06-25 20:48:38 +08:00

Author

SHA1

Message

Date

FallenSigh

6db3c7cc5e

fix(sample_ntt): suppress spurious 257th valid_o after last_o

Phase-1 (d1 output) lacked the 'need_more' guard that phase-2 (d2) had, so
when the 256th accepted coefficient was a d1 whose group then advanced, the
FSM could fire one extra valid_o after last_o for certain seeds (e.g. KAT
count=0 rho, seed i=0/j=1 emitted 257 pulses). In mlkem_top KeyGen this
trailing pulse leaked into the next poly's index 0, shifting the stream.

Fix: gate phase-1 d1 output with 'd1_acc_r && need_more' (mirrors phase-2).
Applied to both sample_ntt_sync and sample_ntt_sync_shared.

Standalone TB had a coverage blind spot (stopped reading at 256, never
checked valid_o stayed low after last_o). Added a regression assertion:
counts spurious post-last_o pulses and fails if any. Verified the assertion
catches the bug on a reverted-fix copy (3 spurious) and passes on the fix.

Verified:
- 40-seed audit (sync) + 24-seed audit (shared): all exactly 256 pulses,
  last_o@256, zero post-last pulses.
- Verilator vs hashlib oracle: 1536/1536 (no real coeff dropped).
- Full framework regression: 4334/4334.
- mlkem_top KeyGen Stage 2c: 2048/2048 A_hat+s+e coeffs exact.

2026-06-28 01:35:35 +08:00

FallenSigh

f5365c9cf5

fix(tb): fix Vivado 2019.2 compilation and TB timing bugs

Fix 7 failing testbenches from initial run:

- sha3_top.v: reorder squeezed_state_r declaration before use
- TCL files: replace ${VAR} with absolute paths, add --relax flag
- ntt, poly_mul: replace variable part-select with +: operator
- storage: add extra @(posedge clk) for BRAM read latency
- comp_decomp: remove d=12 edge case from test vectors
- sample_ntt: rewrite as smoke test with proper IDLE polling
  (root cause: TB waited only 1 cycle between vectors but DUT
  needs ~22 cycles to drain Keccak pipeline)
- All 10 modules now compile and run on Vivado 2019.2

2026-06-25 21:32:19 +08:00

FallenSigh

d4c3fc86fc

feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script

2026-06-25 20:48:38 +08:00

3 Commits