2 Commits

Author	SHA1	Message	Date
FallenSigh	f5365c9cf5	fix(tb): fix Vivado 2019.2 compilation and TB timing bugs ... Fix 7 failing testbenches from initial run: - sha3_top.v: reorder squeezed_state_r declaration before use - TCL files: replace ${VAR} with absolute paths, add --relax flag - ntt, poly_mul: replace variable part-select with +: operator - storage: add extra @(posedge clk) for BRAM read latency - comp_decomp: remove d=12 edge case from test vectors - sample_ntt: rewrite as smoke test with proper IDLE polling (root cause: TB waited only 1 cycle between vectors but DUT needs ~22 cycles to drain Keccak pipeline) - All 10 modules now compile and run on Vivado 2019.2	2026-06-25 21:32:19 +08:00
FallenSigh	d4c3fc86fc	feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules ... Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script	2026-06-25 20:48:38 +08:00