mlkem-sync

fallensigh/mlkem-sync

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Author	SHA1	Message	Date
FallenSigh	4997657d7e	test(comp_decomp): add ML-KEM-1024 d=11/d=5 compress/decompress cases Adds 4 Verilator cases covering d_u=11 and d_v=5 (ML-KEM-1024), which the RTL already supports (d is 5-bit, products fit 24 bits). comp_decomp now 120/120 vectors. Also ignore .omo/ session runtime cache and archive the 06-27-sha3-g-test-specific-input trellis task. Verified all 10 modules pass both frameworks: - Verilator: 4334/4334 vectors - XSIM (Vivado 2019.2): all 11 testbenches green, separate committed vectors Oracles independently cross-checked vs hashlib (G/H/J/PRF) and FIPS 203 Alg 7/8/9/10/12 (sample_ntt, sample_cbd, ntt, poly_mul).	2026-06-27 21:04:57 +08:00
FallenSigh	8fdf944555	feat: init mlkem project with Verilator test framework - sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented	2026-06-24 19:43:29 +08:00

Author

SHA1

Message

Date

FallenSigh

4997657d7e

test(comp_decomp): add ML-KEM-1024 d=11/d=5 compress/decompress cases

Adds 4 Verilator cases covering d_u=11 and d_v=5 (ML-KEM-1024), which the
RTL already supports (d is 5-bit, products fit 24 bits). comp_decomp now
120/120 vectors. Also ignore .omo/ session runtime cache and archive the
06-27-sha3-g-test-specific-input trellis task.

Verified all 10 modules pass both frameworks:
- Verilator: 4334/4334 vectors
- XSIM (Vivado 2019.2): all 11 testbenches green, separate committed vectors
Oracles independently cross-checked vs hashlib (G/H/J/PRF) and FIPS 203
Alg 7/8/9/10/12 (sample_ntt, sample_cbd, ntt, poly_mul).

2026-06-27 21:04:57 +08:00

FallenSigh

8fdf944555

feat: init mlkem project with Verilator test framework

- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented

2026-06-24 19:43:29 +08:00

2 Commits