mlkem-sync

fallensigh/mlkem-sync

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Author	SHA1	Message	Date
FallenSigh	4d3adc6b57	refactor(kg): split polymem into 3 banks {a, se, t} (async, stage 2a) Replace the single async-read polymem[0:28*256-1] with 3 polynomial-indexed banks (bank_a A_hat / bank_se s_hat\|\|e_hat / bank_t t_hat), addressed by abs_slot - base_slot. Still async-read here -- a pure refactor that validates bank sizing and base-relative addressing with zero timing change before stage 2b converts them to registered sd_bram + read-ahead pipelines. 11/11 KAT PASS, byte-exact, 0 file-not-found.	2026-06-28 15:55:26 +08:00
FallenSigh	8fdf944555	feat: init mlkem project with Verilator test framework - sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented	2026-06-24 19:43:29 +08:00

Author

SHA1

Message

Date

FallenSigh

4d3adc6b57

refactor(kg): split polymem into 3 banks {a, se, t} (async, stage 2a)

Replace the single async-read polymem[0:28*256-1] with 3 polynomial-indexed
banks (bank_a A_hat / bank_se s_hat||e_hat / bank_t t_hat), addressed by
abs_slot - base_slot. Still async-read here -- a pure refactor that validates
bank sizing and base-relative addressing with zero timing change before
stage 2b converts them to registered sd_bram + read-ahead pipelines.

11/11 KAT PASS, byte-exact, 0 file-not-found.

2026-06-28 15:55:26 +08:00

FallenSigh

8fdf944555

feat: init mlkem project with Verilator test framework

- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented

2026-06-24 19:43:29 +08:00

2 Commits