4997657d7e
test(comp_decomp): add ML-KEM-1024 d=11/d=5 compress/decompress cases
...
Adds 4 Verilator cases covering d_u=11 and d_v=5 (ML-KEM-1024), which the
RTL already supports (d is 5-bit, products fit 24 bits). comp_decomp now
120/120 vectors. Also ignore .omo/ session runtime cache and archive the
06-27-sha3-g-test-specific-input trellis task.
Verified all 10 modules pass both frameworks:
- Verilator: 4334/4334 vectors
- XSIM (Vivado 2019.2): all 11 testbenches green, separate committed vectors
Oracles independently cross-checked vs hashlib (G/H/J/PRF) and FIPS 203
Alg 7/8/9/10/12 (sample_ntt, sample_cbd, ntt, poly_mul).
2026-06-27 21:04:57 +08:00
030d032657
chore(task): archive 06-27-kg-en-de-separate-tb
2026-06-27 02:27:28 +08:00
d7e65e2cf8
chore(task): archive 06-27-vivado-project-tcl
2026-06-27 01:51:46 +08:00
d61efc96c3
chore(task): archive 06-27-fix-tb-strict-compare
2026-06-27 01:48:14 +08:00
e3470c92e1
chore(task): archive 06-27-fix-kg-compute
2026-06-27 01:38:45 +08:00
09efbef423
chore(task): archive 06-27-mlkem-top-tb
2026-06-27 01:07:40 +08:00
e3e02fc7ee
chore(task): archive 06-26-mlkem-top-integration
2026-06-26 03:35:47 +08:00
92f851da84
chore: record journal
2026-06-25 22:23:15 +08:00
37c4df2582
chore(task): archive 06-25-fix-tb-failures
2026-06-25 22:23:08 +08:00
06d771f4bc
chore: record journal
2026-06-25 20:59:39 +08:00
171ffd91d3
chore(task): archive 06-25-vivado-verilog-tb
2026-06-25 20:59:32 +08:00
79653ac3a5
fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh
...
- Replace -include_dirs . with -i . (Vivado 2019.2 syntax)
- Add --timescale 1ns/1ps to all xelab commands
- Add LD_PRELOAD comment for ncurses compatibility
- Add run_tb.sh convenience script
Usage: ./run_tb.sh mod_add
./run_tb.sh --list
- Update spec with Vivado 2019.2 compatibility notes
2026-06-25 20:53:47 +08:00
52c625b3ef
docs(spec): add XSIM testbench conventions to RTL spec
...
Document Vivado XSIM Verilog testbench conventions:
- File naming, directory structure, TB template
- Clock/reset patterns, valid/ready protocol
- Vector format for
- xsim_run.tcl conventions with -include_dirs requirement
- gen_vectors.py conventions (stdlib only, bit ordering)
- Common mistakes checklist
2026-06-25 20:48:44 +08:00
8fdf944555
feat: init mlkem project with Verilator test framework
...
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented
2026-06-24 19:43:29 +08:00
