3 Commits

Author	SHA1	Message	Date
FallenSigh	79653ac3a5	fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh ... - Replace -include_dirs . with -i . (Vivado 2019.2 syntax) - Add --timescale 1ns/1ps to all xelab commands - Add LD_PRELOAD comment for ncurses compatibility - Add run_tb.sh convenience script Usage: ./run_tb.sh mod_add ./run_tb.sh --list - Update spec with Vivado 2019.2 compatibility notes	2026-06-25 20:53:47 +08:00
FallenSigh	d4c3fc86fc	feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules ... Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script	2026-06-25 20:48:38 +08:00
FallenSigh	5941fee980	feat(phase1): implement RNG, SampleCBD, SampleNTT modules + xsim TBs ... Phase 1 complete — all 4 leaf modules verified: - rng_sync.v: 256-bit Galois LFSR PRNG (10/10 PASS) - sample_cbd_sync.v: CBD sampler with keccak_core PRF (2560/2560 PASS) - sample_ntt_sync.v: SHAKE-128 rejection sampling for A matrix (1536/1536 PASS) - xsim Verilog TBs for sha3 module (tb_sha3_xsim.v, tb_sha3_xsim_simple.v, tb_keccak_core_xsim.v)	2026-06-24 21:32:53 +08:00