mlkem-sync

fallensigh/mlkem-sync

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Author	SHA1	Message	Date
FallenSigh	79653ac3a5	fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh - Replace -include_dirs . with -i . (Vivado 2019.2 syntax) - Add --timescale 1ns/1ps to all xelab commands - Add LD_PRELOAD comment for ncurses compatibility - Add run_tb.sh convenience script Usage: ./run_tb.sh mod_add ./run_tb.sh --list - Update spec with Vivado 2019.2 compatibility notes	2026-06-25 20:53:47 +08:00
FallenSigh	d4c3fc86fc	feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script	2026-06-25 20:48:38 +08:00
FallenSigh	39dd36994b	feat(poly_mul): implement synchronous PolyMul with base-case multiply Phase 2.2: NTT-domain polynomial pointwise multiplication. - basecase_mul.v: degree-1 base-case multiply (c0,c1) with Barrett - poly_mul_zeta_rom.v: 128-entry zeta ROM for PolyMul - poly_mul_sync.v: FSM (IDLE→LOAD 256 cycles→COMPUTE 256 cycles→DONE) Verified: 5/5 vectors bit-exact vs Python PolyMul reference	2026-06-24 23:10:18 +08:00

Author

SHA1

Message

Date

FallenSigh

79653ac3a5

fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh

- Replace -include_dirs . with -i . (Vivado 2019.2 syntax)
- Add --timescale 1ns/1ps to all xelab commands
- Add LD_PRELOAD comment for ncurses compatibility
- Add run_tb.sh convenience script
  Usage: ./run_tb.sh mod_add
         ./run_tb.sh --list
- Update spec with Vivado 2019.2 compatibility notes

2026-06-25 20:53:47 +08:00

FallenSigh

d4c3fc86fc

feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script

2026-06-25 20:48:38 +08:00

FallenSigh

39dd36994b

feat(poly_mul): implement synchronous PolyMul with base-case multiply

Phase 2.2: NTT-domain polynomial pointwise multiplication.
- basecase_mul.v: degree-1 base-case multiply (c0,c1) with Barrett
- poly_mul_zeta_rom.v: 128-entry zeta ROM for PolyMul
- poly_mul_sync.v: FSM (IDLE→LOAD 256 cycles→COMPUTE 256 cycles→DONE)

Verified: 5/5 vectors bit-exact vs Python PolyMul reference

2026-06-24 23:10:18 +08:00

3 Commits