mlkem-sync

fallensigh/mlkem-sync

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Author	SHA1	Message	Date
FallenSigh	79653ac3a5	fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh - Replace -include_dirs . with -i . (Vivado 2019.2 syntax) - Add --timescale 1ns/1ps to all xelab commands - Add LD_PRELOAD comment for ncurses compatibility - Add run_tb.sh convenience script Usage: ./run_tb.sh mod_add ./run_tb.sh --list - Update spec with Vivado 2019.2 compatibility notes	2026-06-25 20:53:47 +08:00
FallenSigh	d4c3fc86fc	feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules Add file-based vector testbenches ( + ) for: - mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync - s_bram/sd_bram, sha3_chain_top - ntt_core, poly_mul_sync - sample_cbd_sync, sample_ntt_sync Each module includes: - tb_<module>_xsim.v: Vivado XSIM testbench - gen_vectors.py: Python vector generator (stdlib only) - vectors/<module>_input.hex: test input vectors - xsim_run.tcl: compile + elaborate + simulate script	2026-06-25 20:48:38 +08:00
FallenSigh	c4cd10c2c1	feat(ntt): implement synchronous NTT core with Barrett modular reduction Phase 2.1: Merged Path00+Path01 NTT engine. - barrett_mul.v: Barrett modular multiplication (a·b mod 3329) - butterfly_unit.v: Cooley-Tukey/Gentleman-Sande butterfly - zeta_rom.v: 128-entry ROM with bit-reversed roots of unity - ntt_core.v: 7-layer NTT FSM, 256×12-bit register file - ntt_sync.v: valid/ready streaming wrapper Verified: 13/13 vectors bit-exact vs Python NTT/NTTInverse	2026-06-24 22:51:14 +08:00

Author

SHA1

Message

Date

FallenSigh

79653ac3a5

fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh

- Replace -include_dirs . with -i . (Vivado 2019.2 syntax)
- Add --timescale 1ns/1ps to all xelab commands
- Add LD_PRELOAD comment for ncurses compatibility
- Add run_tb.sh convenience script
  Usage: ./run_tb.sh mod_add
         ./run_tb.sh --list
- Update spec with Vivado 2019.2 compatibility notes

2026-06-25 20:53:47 +08:00

FallenSigh

d4c3fc86fc

feat(tb): add Vivado XSIM Verilog testbenches for all 10 sync modules

Add file-based vector testbenches ( + ) for:
- mod_add_sync, rng_sync, poly_arith_sync, comp_decomp_sync
- s_bram/sd_bram, sha3_chain_top
- ntt_core, poly_mul_sync
- sample_cbd_sync, sample_ntt_sync

Each module includes:
- tb_<module>_xsim.v: Vivado XSIM testbench
- gen_vectors.py: Python vector generator (stdlib only)
- vectors/<module>_input.hex: test input vectors
- xsim_run.tcl: compile + elaborate + simulate script

2026-06-25 20:48:38 +08:00

FallenSigh

c4cd10c2c1

feat(ntt): implement synchronous NTT core with Barrett modular reduction

Phase 2.1: Merged Path00+Path01 NTT engine.
- barrett_mul.v: Barrett modular multiplication (a·b mod 3329)
- butterfly_unit.v: Cooley-Tukey/Gentleman-Sande butterfly
- zeta_rom.v: 128-entry ROM with bit-reversed roots of unity
- ntt_core.v: 7-layer NTT FSM, 256×12-bit register file
- ntt_sync.v: valid/ready streaming wrapper

Verified: 13/13 vectors bit-exact vs Python NTT/NTTInverse

2026-06-24 22:51:14 +08:00

3 Commits