|
|
06d771f4bc
|
chore: record journal
|
2026-06-25 20:59:39 +08:00 |
|
|
|
171ffd91d3
|
chore(task): archive 06-25-vivado-verilog-tb
|
2026-06-25 20:59:32 +08:00 |
|
|
|
79653ac3a5
|
fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh
- Replace -include_dirs . with -i . (Vivado 2019.2 syntax)
- Add --timescale 1ns/1ps to all xelab commands
- Add LD_PRELOAD comment for ncurses compatibility
- Add run_tb.sh convenience script
Usage: ./run_tb.sh mod_add
./run_tb.sh --list
- Update spec with Vivado 2019.2 compatibility notes
|
2026-06-25 20:53:47 +08:00 |
|
|
|
52c625b3ef
|
docs(spec): add XSIM testbench conventions to RTL spec
Document Vivado XSIM Verilog testbench conventions:
- File naming, directory structure, TB template
- Clock/reset patterns, valid/ready protocol
- Vector format for
- xsim_run.tcl conventions with -include_dirs requirement
- gen_vectors.py conventions (stdlib only, bit ordering)
- Common mistakes checklist
|
2026-06-25 20:48:44 +08:00 |
|
|
|
8fdf944555
|
feat: init mlkem project with Verilator test framework
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented
|
2026-06-24 19:43:29 +08:00 |
|
