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92f851da84
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chore: record journal
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2026-06-25 22:23:15 +08:00 |
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37c4df2582
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chore(task): archive 06-25-fix-tb-failures
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2026-06-25 22:23:08 +08:00 |
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06d771f4bc
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chore: record journal
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2026-06-25 20:59:39 +08:00 |
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171ffd91d3
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chore(task): archive 06-25-vivado-verilog-tb
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2026-06-25 20:59:32 +08:00 |
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79653ac3a5
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fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh
- Replace -include_dirs . with -i . (Vivado 2019.2 syntax)
- Add --timescale 1ns/1ps to all xelab commands
- Add LD_PRELOAD comment for ncurses compatibility
- Add run_tb.sh convenience script
Usage: ./run_tb.sh mod_add
./run_tb.sh --list
- Update spec with Vivado 2019.2 compatibility notes
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2026-06-25 20:53:47 +08:00 |
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52c625b3ef
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docs(spec): add XSIM testbench conventions to RTL spec
Document Vivado XSIM Verilog testbench conventions:
- File naming, directory structure, TB template
- Clock/reset patterns, valid/ready protocol
- Vector format for
- xsim_run.tcl conventions with -include_dirs requirement
- gen_vectors.py conventions (stdlib only, bit ordering)
- Common mistakes checklist
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2026-06-25 20:48:44 +08:00 |
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8fdf944555
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feat: init mlkem project with Verilator test framework
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented
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2026-06-24 19:43:29 +08:00 |
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