|
|
030d032657
|
chore(task): archive 06-27-kg-en-de-separate-tb
|
2026-06-27 02:27:28 +08:00 |
|
|
|
d7e65e2cf8
|
chore(task): archive 06-27-vivado-project-tcl
|
2026-06-27 01:51:46 +08:00 |
|
|
|
d61efc96c3
|
chore(task): archive 06-27-fix-tb-strict-compare
|
2026-06-27 01:48:14 +08:00 |
|
|
|
e3470c92e1
|
chore(task): archive 06-27-fix-kg-compute
|
2026-06-27 01:38:45 +08:00 |
|
|
|
09efbef423
|
chore(task): archive 06-27-mlkem-top-tb
|
2026-06-27 01:07:40 +08:00 |
|
|
|
e3e02fc7ee
|
chore(task): archive 06-26-mlkem-top-integration
|
2026-06-26 03:35:47 +08:00 |
|
|
|
37c4df2582
|
chore(task): archive 06-25-fix-tb-failures
|
2026-06-25 22:23:08 +08:00 |
|
|
|
171ffd91d3
|
chore(task): archive 06-25-vivado-verilog-tb
|
2026-06-25 20:59:32 +08:00 |
|
|
|
8fdf944555
|
feat: init mlkem project with Verilator test framework
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented
|
2026-06-24 19:43:29 +08:00 |
|
