mlkem-sync

fallensigh/mlkem-sync

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Author	SHA1	Message	Date
FallenSigh	717a9929b6	fix(rtl,scripts): replace combinational divider with Barrett multiplication, add synthesis include_dirs, set 50MHz clock - Replace / and % operators in comp_decomp_sync with Barrett multiply-by-reciprocal (dividend * 5039 >> 24) + correction step. Eliminates ~100 CARRY4 divider chain. - Add include_dirs for sources_1 fileset so Windows Vivado synthesis finds defines.vh. - Change CLK_PERIOD from 10.0 (100MHz) to 40.0 (50MHz) to reflect actual target.	2026-06-30 00:23:43 +08:00
FallenSigh	8fdf944555	feat: init mlkem project with Verilator test framework - sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented	2026-06-24 19:43:29 +08:00

Author

SHA1

Message

Date

FallenSigh

717a9929b6

fix(rtl,scripts): replace combinational divider with Barrett multiplication, add synthesis include_dirs, set 50MHz clock

- Replace / and % operators in comp_decomp_sync with Barrett multiply-by-reciprocal
  (dividend * 5039 >> 24) + correction step. Eliminates ~100 CARRY4 divider chain.
- Add include_dirs for sources_1 fileset so Windows Vivado synthesis finds defines.vh.
- Change CLK_PERIOD from 10.0 (100MHz) to 40.0 (50MHz) to reflect actual target.

2026-06-30 00:23:43 +08:00

FallenSigh

8fdf944555

feat: init mlkem project with Verilator test framework

- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented

2026-06-24 19:43:29 +08:00

2 Commits