feat(sha3_chain): add simple SHA3_G integration test
Phase 3.2: Verifies module chaining works. - sha3_chain_top.v: 3-state FSM (IDLE→BUSY→DONE), feeds d_in→sha3_top(G) - Captures rho[255:0] and sigma[511:256] from SHA3-512 output - Verified: 3/3 bit-exact vs Python G(d||k=2) reference KG full-path FSM (~11 module chain) deferred — too complex for single dispatch.
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179
sync_rtl/sha3_chain/TB/tb_sha3_chain.cpp
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179
sync_rtl/sha3_chain/TB/tb_sha3_chain.cpp
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// tb_sha3_chain.cpp - Verilator C++ testbench for sha3_chain_top
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//
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// Reads test vectors from +VECTOR_FILE= plusarg.
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// Format: one 64-char hex string per line (256-bit d).
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//
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// Drives d_in, asserts start_i, waits for done_o,
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// prints "RESULT: RHO_HEX SIGMA_HEX\n" to stdout.
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//
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// Clock: 10ns period. Reset: 2 cycles.
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#include <iostream>
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#include <fstream>
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#include <string>
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#include <cstdlib>
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#include <cstdint>
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#include "Vsha3_chain_top.h"
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#include "verilated.h"
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#define CLK_PERIOD_NS 10.0
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#define TIMEOUT_CYCLES 500000
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static vluint64_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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// One full clock cycle (both edges + eval)
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static void posedge(Vsha3_chain_top* dut) {
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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}
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static int hex_char_to_nibble(char c) {
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if (c >= '0' && c <= '9') return c - '0';
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if (c >= 'A' && c <= 'F') return c - 'A' + 10;
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if (c >= 'a' && c <= 'f') return c - 'a' + 10;
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return 0;
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}
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// Parse 64-char hex string into 8 x 32-bit WData words (256 bits).
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// Hex is MSB-first (leftmost = bits [255:252]).
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// data[0] = bits[31:0], data[7] = bits[255:224].
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static void hex_to_256(const std::string& hex, uint32_t data_words[8]) {
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for (int w = 0; w < 8; w++) data_words[w] = 0;
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int nibble_idx = 0;
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for (int i = (int)hex.length() - 1; i >= 0; i--) {
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char c = hex[i];
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if (c == ' ' || c == '\t') continue;
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int nib = hex_char_to_nibble(c);
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int word_idx = nibble_idx / 8;
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int shift = (nibble_idx % 8) * 4;
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if (word_idx < 8) {
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data_words[word_idx] |= ((uint32_t)nib << shift);
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}
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nibble_idx++;
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}
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}
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// Print rho_out and sigma_out as hex (MSB-first), space-separated.
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// rho[0]=bits[31:0], rho[7]=bits[255:224]
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// sigma[0]=bits[31:0], sigma[7]=bits[255:224]
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static void print_256_hex(uint32_t data_words[8]) {
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for (int w = 7; w >= 0; w--) {
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uint32_t val = data_words[w];
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for (int j = 28; j >= 0; j -= 4) {
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printf("%01X", (int)((val >> j) & 0xF));
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}
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}
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}
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int main(int argc, char** argv) {
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Verilated::commandArgs(argc, argv);
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// Parse +VECTOR_FILE= plusarg
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const char* vector_file = NULL;
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for (int i = 1; i < argc; i++) {
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std::string arg(argv[i]);
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if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
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vector_file = argv[i] + 13;
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}
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}
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if (!vector_file) {
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std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
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return 1;
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}
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std::ifstream infile(vector_file);
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if (!infile.is_open()) {
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std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
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return 1;
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}
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// Instantiate DUT
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Vsha3_chain_top* dut = new Vsha3_chain_top;
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// Initialize
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dut->clk = 0;
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dut->rst_n = 0;
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for (int w = 0; w < 8; w++) dut->d_in[w] = 0;
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dut->start_i = 0;
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// Reset: 2 full cycles
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for (int i = 0; i < 2; i++) posedge(dut);
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dut->rst_n = 1;
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std::string line;
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vluint64_t cycle = 0;
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int vec_count = 0;
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while (std::getline(infile, line)) {
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if (line.empty() || line[0] == '#') continue;
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std::string d_hex = line;
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// Trim trailing whitespace
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while (!d_hex.empty() && (d_hex.back() == ' ' || d_hex.back() == '\t' || d_hex.back() == '\r'))
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d_hex.pop_back();
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// Parse d
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uint32_t d_words[8];
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hex_to_256(d_hex, d_words);
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for (int w = 0; w < 8; w++) dut->d_in[w] = d_words[w];
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// Assert start_i
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dut->start_i = 1;
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// One cycle with start_i=1
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cycle++;
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posedge(dut);
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// De-assert start_i
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dut->start_i = 0;
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// Wait for done_o
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while (!dut->done_o) {
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posedge(dut);
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cycle++;
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if (cycle > TIMEOUT_CYCLES) {
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std::cerr << "ERROR: Timeout waiting for done_o (vec " << vec_count << ")" << std::endl;
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goto done;
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}
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}
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// Read outputs
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uint32_t rho_words[8], sigma_words[8];
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for (int w = 0; w < 8; w++) {
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rho_words[w] = dut->rho_out[w];
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sigma_words[w] = dut->sigma_out[w];
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}
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printf("RESULT: ");
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print_256_hex(rho_words);
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printf(" ");
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print_256_hex(sigma_words);
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printf("\n");
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// One cycle with done_o high, then start_i must be low to return to IDLE
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posedge(dut);
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cycle++;
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vec_count++;
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}
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done:
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infile.close();
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delete dut;
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if (vec_count == 0) {
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std::cerr << "ERROR: No vectors processed" << std::endl;
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return 1;
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}
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return 0;
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}
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93
sync_rtl/sha3_chain/sha3_chain_top.v
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93
sync_rtl/sha3_chain/sha3_chain_top.v
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@@ -0,0 +1,93 @@
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// sha3_chain_top.v - Simple integration module: d → SHA3_G(d||k=2)
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//
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// Feeds external 256-bit d to sha3_top in G mode with k=2, captures
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// rho (first 256 bits) and sigma (next 256 bits) from the hash output.
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//
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// 3-state FSM: IDLE → BUSY → DONE
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//
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// Interface:
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// clk, rst_n - clock, active-low reset
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// d_in[255:0] - 256-bit d input (external, NOT from RNG)
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// start_i - start computation
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// done_o - computation complete
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// rho_out - G output first 256 bits
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// sigma_out - G output next 256 bits
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module sha3_chain_top (
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input clk,
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input rst_n,
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input [255:0] d_in,
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input start_i,
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output done_o,
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output [255:0] rho_out,
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output [255:0] sigma_out
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);
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localparam ST_IDLE = 2'd0;
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localparam ST_BUSY = 2'd1;
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localparam ST_DONE = 2'd2;
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reg [1:0] state_r, state_next;
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// ── sha3_top signals ──
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wire [511:0] sha3_data_i;
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wire sha3_valid_i;
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wire sha3_ready_o;
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wire [511:0] sha3_hash_o;
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wire sha3_valid_o;
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// data_i = {248'b0, k=8'd2, d_in}
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assign sha3_data_i = {248'b0, 8'd2, d_in};
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sha3_top u_sha3 (
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.clk (clk),
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.rst_n (rst_n),
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.mode (2'b00), // G mode (SHA3-512)
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.data_i (sha3_data_i),
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.valid_i (sha3_valid_i),
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.ready_o (sha3_ready_o),
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.hash_o (sha3_hash_o),
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.valid_o (sha3_valid_o),
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.ready_i (1'b1) // always accept output
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);
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// valid_i: assert when IDLE + start_i + sha3 ready
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assign sha3_valid_i = (state_r == ST_IDLE) && start_i && sha3_ready_o;
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// done_o
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assign done_o = (state_r == ST_DONE);
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// ── output registers ──
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reg [255:0] rho_out_r, sigma_out_r;
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assign rho_out = rho_out_r;
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assign sigma_out = sigma_out_r;
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// ── FSM combinational next-state ──
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always @(*) begin
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state_next = state_r;
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case (state_r)
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ST_IDLE: if (start_i && sha3_ready_o) state_next = ST_BUSY;
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ST_BUSY: if (sha3_valid_o) state_next = ST_DONE;
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ST_DONE: if (!start_i) state_next = ST_IDLE;
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default: state_next = ST_IDLE;
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endcase
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end
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// ── sequential logic ──
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state_r <= ST_IDLE;
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rho_out_r <= 256'd0;
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sigma_out_r <= 256'd0;
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end else begin
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state_r <= state_next;
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// Capture output when BUSY → DONE
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if (state_r == ST_BUSY && sha3_valid_o) begin
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rho_out_r <= sha3_hash_o[255:0];
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sigma_out_r <= sha3_hash_o[511:256];
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end
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end
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end
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endmodule
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