feat: init mlkem project with Verilator test framework

- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented

test_framework/modules/mod_add/test_plan.json

@@ -0,0 +1,17 @@
+{
+  "module": "mod_add",
+  "rtl_top": "sync_rtl/mod_add/mod_add_sync.v",
+  "rtl_deps": ["sync_rtl/common/pipeline_reg.v"],
+  "tb_cpp": "sync_rtl/mod_add/TB/tb_mod_add.cpp",
+  "simulator": "verilator",
+  "timeout_s": 30,
+  "cases": [
+    {
+      "id": "basic",
+      "description": "Random (a+b) mod Q pairs, no overflow, with overflow, edge cases",
+      "params": {},
+      "num_vectors": 50,
+      "tolerance": "bit_exact"
+    }
+  ]
+}