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feat: init mlkem project with Verilator test framework

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- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented
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FallenSigh
2026-06-24 19:43:29 +08:00
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# Journal - FallenSigh (Part 1)
> AI development session journal
> Started: 2026-06-24
---