docs(spec): add XSIM testbench conventions to RTL spec

Document Vivado XSIM Verilog testbench conventions:
- File naming, directory structure, TB template
- Clock/reset patterns, valid/ready protocol
- Vector format for
- xsim_run.tcl conventions with -include_dirs requirement
- gen_vectors.py conventions (stdlib only, bit ordering)
- Common mistakes checklist

.trellis/spec/rtl/index.md

@@ -0,0 +1,14 @@
+# RTL Specifications
+
+## Pre-Development Checklist
+
+Before writing RTL code or testbenches, read:
+1. [Verilator Conventions](./verilator-conventions.md) — for C++ Verilator testbenches
+2. [XSIM Testbench Conventions](./xsim-tb-conventions.md) — for Vivado XSIM Verilog testbenches
+
+## Files
+
+| File | Purpose |
+|------|---------|
+| `verilator-conventions.md` | Verilator 5.046 C++ testbench conventions (clock, timing, valid/ready protocol) |
+| `xsim-tb-conventions.md` | Vivado XSIM Verilog testbench conventions (template, vector format, TCL scripts) |