test(comp_decomp): add ML-KEM-1024 d=11/d=5 compress/decompress cases

Adds 4 Verilator cases covering d_u=11 and d_v=5 (ML-KEM-1024), which the
RTL already supports (d is 5-bit, products fit 24 bits). comp_decomp now
120/120 vectors. Also ignore .omo/ session runtime cache and archive the
06-27-sha3-g-test-specific-input trellis task.

Verified all 10 modules pass both frameworks:
- Verilator: 4334/4334 vectors
- XSIM (Vivado 2019.2): all 11 testbenches green, separate committed vectors
Oracles independently cross-checked vs hashlib (G/H/J/PRF) and FIPS 203
Alg 7/8/9/10/12 (sample_ntt, sample_cbd, ntt, poly_mul).

test_framework/modules/comp_decomp/test_plan.json

@@ -33,6 +33,34 @@
       "params": {"mode": "decompress", "d": 4},
       "num_vectors": 10,
       "tolerance": "bit_exact"
+    },
+    {
+      "id": "compress_du11",
+      "description": "Compress with du=11 (ML-KEM-1024)",
+      "params": {"mode": "compress", "d": 11},
+      "num_vectors": 20,
+      "tolerance": "bit_exact"
+    },
+    {
+      "id": "compress_dv5",
+      "description": "Compress with dv=5 (ML-KEM-1024)",
+      "params": {"mode": "compress", "d": 5},
+      "num_vectors": 20,
+      "tolerance": "bit_exact"
+    },
+    {
+      "id": "decompress_du11",
+      "description": "Decompress with du=11 (ML-KEM-1024)",
+      "params": {"mode": "decompress", "d": 11},
+      "num_vectors": 10,
+      "tolerance": "bit_exact"
+    },
+    {
+      "id": "decompress_dv5",
+      "description": "Decompress with dv=5 (ML-KEM-1024)",
+      "params": {"mode": "decompress", "d": 5},
+      "num_vectors": 10,
+      "tolerance": "bit_exact"
     }
   ]
 }