test(comp_decomp): add ML-KEM-1024 d=11/d=5 compress/decompress cases

Adds 4 Verilator cases covering d_u=11 and d_v=5 (ML-KEM-1024), which the
RTL already supports (d is 5-bit, products fit 24 bits). comp_decomp now
120/120 vectors. Also ignore .omo/ session runtime cache and archive the
06-27-sha3-g-test-specific-input trellis task.

Verified all 10 modules pass both frameworks:
- Verilator: 4334/4334 vectors
- XSIM (Vivado 2019.2): all 11 testbenches green, separate committed vectors
Oracles independently cross-checked vs hashlib (G/H/J/PRF) and FIPS 203
Alg 7/8/9/10/12 (sample_ntt, sample_cbd, ntt, poly_mul).

.trellis/tasks/06-27-sha3-g-test-specific-input/check.jsonl

@@ -0,0 +1 @@
+{"file": ".trellis/spec/rtl/xsim-tb-conventions.md", "reason": "检查 testbench 修改是否符合 XSIM 规范"}

.trellis/tasks/06-27-sha3-g-test-specific-input/implement.jsonl

@@ -0,0 +1 @@
+{"file": ".trellis/spec/rtl/xsim-tb-conventions.md", "reason": "遵循 XSIM testbench 编写规范：时钟、复位、DUT驱动协议"}

.trellis/tasks/06-27-sha3-g-test-specific-input/prd.md

@@ -0,0 +1,30 @@
+# 修改 sha3 TB 测试 G 模式指定输入
+
+## 需求
+
+修改 `sync_rtl/sha3/TB/tb_sha3_xsim_simple.v`，将其中硬编码的测试向量替换为指定的 d、k 值，测试 sha3_top 的 G (SHA3-512) 模式。
+
+## 测试输入
+
+```
+d = 0x6dbbc4375136df3b07f7c70e639e223e177e7fd53b161b3f4d57791794f12624  (256-bit)
+k = 2  (8-bit)
+mode = G (2'b00)
+```
+
+在 RTL 中，G 模式的输入格式为 `data_i[263:0] = {d[255:0], k[7:0]}`（d 在低位，k 在高位），即：
+
+```
+data_i = {248'd0, 8'd2, 256'h6dbbc4375136df3b07f7c70e639e223e177e7fd53b161b3f4d57791794f12624}
+```
+
+## 修改方案
+
+修改 `tb_sha3_xsim_simple.v`：
+1. 将 `data_i = 512'd0` 替换为指定值 `{248'd0, 8'd2, 256'h6dbbc4375136df3b07f7c70e639e223e177e7fd53b161b3f4d57791794f12624}`
+2. 删除 `G_EXPECTED_HASH` 参数和自检比较逻辑，改为仅打印 `hash_o` 结果
+3. 更新顶部的注释说明
+
+## 预期输出
+
+运行后打印 `hash_o` 的值，可通过 Python 参考实现 `SHA_3.G(d, k)` 交叉验证。

.trellis/tasks/06-27-sha3-g-test-specific-input/task.json

@@ -0,0 +1,26 @@
+{
+  "id": "sha3-g-test-specific-input",
+  "name": "sha3-g-test-specific-input",
+  "title": "修改sha3 TB测试G模式指定输入d=k=2",
+  "description": "",
+  "status": "in_progress",
+  "dev_type": null,
+  "scope": null,
+  "package": null,
+  "priority": "P2",
+  "creator": "FallenSigh",
+  "assignee": "FallenSigh",
+  "createdAt": "2026-06-27",
+  "completedAt": null,
+  "branch": null,
+  "base_branch": "main",
+  "worktree_path": null,
+  "commit": null,
+  "pr_url": null,
+  "subtasks": [],
+  "children": [],
+  "parent": null,
+  "relatedFiles": [],
+  "notes": "",
+  "meta": {}
+}