feat(poly_arith): implement synchronous PolyAdd/PolySub streaming module
Phase 2.3: Polynomial modular addition and subtraction. - poly_arith_sync.v: mode=0 add (a+b mod Q), mode=1 sub (a-b mod Q) - Pure streaming (1 coeff/cycle, no BRAM needed) - Uses pipeline_reg for valid/ready handshake Verified: 10/10 vectors bit-exact vs Python reference
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sync_rtl/poly_arith/TB/tb_poly_arith.cpp
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sync_rtl/poly_arith/TB/tb_poly_arith.cpp
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// tb_poly_arith.cpp - Verilator C++ testbench for poly_arith_sync
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//
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// Reads test vectors from a hex file specified by +VECTOR_FILE= plusarg.
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// Each line: "MODE A0 A1 ... A255 B0 B1 ... B255"
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// MODE: 'A' for add, 'S' for sub
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// A0..A255: 256 hex coefficients (12-bit, 3 hex digits each)
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// B0..B255: 256 hex coefficients
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//
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// Feeds 256 (A, B) pairs through the DUT, collects 256 output coeffs,
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// prints one "RESULT: C0 C1 ... C255" line per vector.
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//
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// Clock: 10 ns period (100 MHz).
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// Reset: 2 cycles low, then high.
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// Timeout: 100,000 cycles.
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#include <iostream>
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#include <fstream>
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#include <string>
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#include <sstream>
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#include <cstdlib>
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#include <vector>
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#include "Vpoly_arith_sync.h"
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#include "verilated.h"
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#define CLK_PERIOD_NS 10.0
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#define TIMEOUT_CYCLES 100000
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static vluint64_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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// Helper: toggle clock (full cycle: low->high->low) with eval
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static void posedge(Vpoly_arith_sync* dut) {
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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}
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int main(int argc, char** argv) {
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Verilated::commandArgs(argc, argv);
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// Parse +VECTOR_FILE= plusarg
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const char* vector_file = NULL;
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for (int i = 1; i < argc; i++) {
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std::string arg(argv[i]);
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if (arg.rfind("+VECTOR_FILE=", 0) == 0) {
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vector_file = argv[i] + 13;
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}
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}
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if (!vector_file) {
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std::cerr << "ERROR: +VECTOR_FILE= not specified" << std::endl;
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return 1;
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}
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std::ifstream infile(vector_file);
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if (!infile.is_open()) {
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std::cerr << "ERROR: Cannot open vector file: " << vector_file << std::endl;
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return 1;
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}
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// Instantiate DUT
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Vpoly_arith_sync* dut = new Vpoly_arith_sync;
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// Initialize
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dut->clk = 0;
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dut->rst_n = 0;
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dut->coeff_a_in = 0;
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dut->coeff_b_in = 0;
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dut->mode = 0;
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dut->valid_i = 0;
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dut->ready_i = 0;
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// Reset: 2 cycles low
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for (int i = 0; i < 4; i++) {
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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dut->clk = !dut->clk;
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main_time += (vluint64_t)(CLK_PERIOD_NS / 2.0);
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dut->eval();
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}
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dut->rst_n = 1;
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// Always ready to receive results
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dut->ready_i = 1;
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std::string line;
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vluint64_t cycle = 0;
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while (std::getline(infile, line)) {
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// Skip empty lines and comments
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if (line.empty() || line[0] == '#') continue;
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// Parse: MODE A0..A255 B0..B255 (513 values on one line)
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std::istringstream iss(line);
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std::string mode_str;
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if (!(iss >> mode_str)) continue;
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// Determine mode
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bool mode_val;
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if (mode_str == "A" || mode_str == "a") {
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mode_val = false;
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} else if (mode_str == "S" || mode_str == "s") {
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mode_val = true;
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} else {
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std::cerr << "ERROR: Unknown mode: " << mode_str << std::endl;
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continue;
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}
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dut->mode = mode_val ? 1 : 0;
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// Read 256 A coeffs
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unsigned int coeff;
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std::vector<unsigned int> a_coeffs, b_coeffs;
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for (int i = 0; i < 256; i++) {
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if (!(iss >> std::hex >> coeff)) {
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std::cerr << "ERROR: Missing A coeff at index " << i << std::endl;
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return 1;
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}
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a_coeffs.push_back(coeff & 0xFFF);
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}
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// Read 256 B coeffs
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for (int i = 0; i < 256; i++) {
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if (!(iss >> std::hex >> coeff)) {
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std::cerr << "ERROR: Missing B coeff at index " << i << std::endl;
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return 1;
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}
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b_coeffs.push_back(coeff & 0xFFF);
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}
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// Feed 256 coefficient pairs and collect results
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std::vector<unsigned int> results;
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for (int i = 0; i < 256; i++) {
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// Drive inputs
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dut->coeff_a_in = a_coeffs[i];
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dut->coeff_b_in = b_coeffs[i];
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dut->valid_i = 1;
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// Posedge: DUT samples input, pipeline_reg captures data, valid_o→1
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posedge(dut);
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dut->valid_i = 0;
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// Read result now (valid_o is high, coeff_out is valid)
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// Posedge: pipeline_reg clears valid_o (ready_i=1), but result
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// is available on coeff_out port (combinational from data_r)
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posedge(dut);
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results.push_back(dut->coeff_out & 0xFFF);
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cycle += 2;
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if (cycle > TIMEOUT_CYCLES) {
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std::cerr << "ERROR: Timeout after " << cycle << " cycles" << std::endl;
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return 1;
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}
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}
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// Print result as one space-separated hex line
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printf("RESULT:");
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for (int i = 0; i < 256; i++) {
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printf(" %03X", results[i]);
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}
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printf("\n");
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}
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infile.close();
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delete dut;
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return 0;
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}
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