chore(task): archive 06-25-vivado-verilog-tb

2026-06-25 20:59:32 +08:00
parent db0a559826
commit 171ffd91d3
4 changed files with 195 additions and 0 deletions
--- a/.trellis/tasks/archive/2026-06/06-25-vivado-verilog-tb/check.jsonl
+++ b/.trellis/tasks/archive/2026-06/06-25-vivado-verilog-tb/check.jsonl
@@ -0,0 +1 @@
+{"file": ".trellis/spec/rtl/verilator-conventions.md", "reason": "RTL conventions for quality checking: clock period, valid/ready timing, testbench structure"}
				`@@ -0,0 +1 @@`
				`{"file": ".trellis/spec/rtl/verilator-conventions.md", "reason": "RTL conventions for quality checking: clock period, valid/ready timing, testbench structure"}`