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feat(create_project): add kg/en/de testbenches to Vivado project

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FallenSigh
2026-06-27 02:33:37 +08:00
parent 030d032657
commit 0b7c76283b
1 changed files with 5 additions and 0 deletions
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create_project.tcl
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@@ -64,6 +64,11 @@ read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/mlkem_top.v
# ── Testbench ── # ── Testbench ──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/TB/tb_mlkem_top_xsim.v read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/TB/tb_mlkem_top_xsim.v
# ── Independent KG / EN / DE testbenches ──
read_verilog -sv ${PROJECT_DIR}/sync_rtl/kg/TB/tb_kg_xsim.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/en/TB/tb_en_xsim.v
read_verilog -sv ${PROJECT_DIR}/sync_rtl/de/TB/tb_de_xsim.v
# ── Include path for `include directives ── # ── Include path for `include directives ──
set_property include_dirs ${PROJECT_DIR} [current_fileset -simset] set_property include_dirs ${PROJECT_DIR} [current_fileset -simset]