diff --git a/create_project.tcl b/create_project.tcl
index c370839..b7eec20 100644
--- a/create_project.tcl
+++ b/create_project.tcl
@@ -64,6 +64,11 @@ read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/mlkem_top.v
 # ── Testbench ──
 read_verilog -sv ${PROJECT_DIR}/sync_rtl/top/TB/tb_mlkem_top_xsim.v
 
+# ── Independent KG / EN / DE testbenches ──
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/kg/TB/tb_kg_xsim.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/en/TB/tb_en_xsim.v
+read_verilog -sv ${PROJECT_DIR}/sync_rtl/de/TB/tb_de_xsim.v
+
 # ── Include path for `include directives ──
 set_property include_dirs ${PROJECT_DIR} [current_fileset -simset]