254 lines
8.4 KiB
Verilog
254 lines
8.4 KiB
Verilog
module axi_dvi #
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(
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parameter WIDTH = 12, // hdata and vdata width (in bits)
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parameter HSIZE = 800, // Horizontal size of visible area
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parameter HFP = 856, // Horizontal front porch
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parameter HSP = 976, // Horizontal sync pulse
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parameter HMAX = 1040, // Horizontal total size
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parameter VSIZE = 600, // Vertical size of visible area
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parameter VFP = 637, // Vertical front porch
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parameter VSP = 643, // Vertical sync pulse
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parameter VMAX = 666, // Vertical total size
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parameter HSPP = 1, // Horizontal sync pulse polarity (1 for positive)
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parameter VSPP = 1 // Vertical sync pulse polarity (1 for positive)
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)
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(
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input s_awvalid,
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output s_awready,
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input [31:0] s_awaddr,
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input [4:0] s_awid,
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input [7:0] s_awlen,
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input [2:0] s_awsize,
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input [1:0] s_awburst,
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input [0:0] s_awlock,
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input [3:0] s_awcache,
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input [2:0] s_awprot,
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input s_wvalid,
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output reg s_wready,
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input [31:0] s_wdata,
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input [3:0] s_wstrb,
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input s_wlast,
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output reg s_bvalid,
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input s_bready,
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output [4:0] s_bid,
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output [1:0] s_bresp,
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input s_arvalid,
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output s_arready,
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input [31:0] s_araddr,
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input [4:0] s_arid,
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input [7:0] s_arlen,
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input [2:0] s_arsize,
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input [1:0] s_arburst,
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input [0:0] s_arlock,
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input [3:0] s_arcache,
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input [2:0] s_arprot,
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output reg s_rvalid,
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input s_rready,
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output reg [31:0] s_rdata,
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output [4:0] s_rid,
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output [1:0] s_rresp,
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output reg s_rlast,
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output video_clk, // Video clock signal
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output hsync, // Horizontal sync signal
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output vsync, // Vertical sync signal
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output data_enable, // Data enable signal
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output [2:0] video_red, // Red color signal (3 bits)
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output [2:0] video_green, // Green color signal (3 bits)
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output [1:0] video_blue, // Blue color signal (2 bits)
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input aclk,
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input aresetn
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);
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reg [31:0] DVI_RECT_DIR,DVI_RECT_L_W,DVI_SQU_DIR,DVI_SQU_R;
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reg busy,write,R_or_W;
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wire ar_enter = s_arvalid & s_arready;
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wire r_retire = s_rvalid & s_rready & s_rlast;
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wire aw_enter = s_awvalid & s_awready;
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wire w_enter = s_wvalid & s_wready & s_wlast;
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wire b_retire = s_bvalid & s_bready;
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assign s_arready = ~busy & (!R_or_W| !s_awvalid);
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assign s_awready = ~busy & ( R_or_W| !s_arvalid);
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always@(posedge aclk)
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if(~aresetn) busy <= 1'b0;
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else if(ar_enter|aw_enter) busy <= 1'b1;
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else if(r_retire|b_retire) busy <= 1'b0;
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reg [3 :0] buf_id;
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reg [31:0] buf_addr;
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reg [7 :0] buf_len;
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reg [2 :0] buf_size;
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reg [1 :0] buf_burst;
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reg buf_lock;
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reg [3 :0] buf_cache;
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reg [2 :0] buf_prot;
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always@(posedge aclk) begin
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if(~aresetn) begin
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R_or_W <= 1'b0;
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buf_id <= 'b0;
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buf_addr <= 'b0;
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buf_len <= 'b0;
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buf_size <= 'b0;
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buf_burst <= 'b0;
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buf_lock <= 'b0;
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buf_cache <= 'b0;
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buf_prot <= 'b0;
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end
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else
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if(ar_enter | aw_enter) begin
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R_or_W <= ar_enter;
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buf_id <= ar_enter ? s_arid : s_awid ;
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buf_addr <= ar_enter ? s_araddr : s_awaddr ;
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buf_len <= ar_enter ? s_arlen : s_awlen ;
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buf_size <= ar_enter ? s_arsize : s_awsize ;
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buf_burst <= ar_enter ? s_arburst: s_awburst;
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buf_lock <= ar_enter ? s_arlock : s_awlock ;
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buf_cache <= ar_enter ? s_arcache: s_awcache;
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buf_prot <= ar_enter ? s_arprot : s_awprot ;
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end
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end
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always@(posedge aclk)
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if(~aresetn) write <= 1'b0;
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else if(aw_enter) write <= 1'b1;
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else if(ar_enter) write <= 1'b0;
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always@(posedge aclk)
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if(~aresetn) s_wready <= 1'b0;
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else if(aw_enter) s_wready <= 1'b1;
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else if(w_enter & s_wlast) s_wready <= 1'b0;
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wire [31:0] rdata_d = buf_addr[15:0] == 16'h0 ? DVI_RECT_DIR :
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buf_addr[15:0] == 16'h4 ? DVI_RECT_L_W :
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buf_addr[15:0] == 16'h8 ? DVI_SQU_DIR :
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buf_addr[15:0] == 16'hc ? DVI_SQU_R :
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32'd0;
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always@(posedge aclk)begin
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if(~aresetn) begin
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s_rdata <= 'b0;
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s_rvalid <= 1'b0;
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s_rlast <= 1'b0;
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end
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else if(busy & !write & !r_retire)
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begin
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s_rdata <= rdata_d;
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s_rvalid <= 1'b1;
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s_rlast <= 1'b1;
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end
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else if(r_retire)
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begin
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s_rvalid <= 1'b0;
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end
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end
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always@(posedge aclk) begin
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if(~aresetn) s_bvalid <= 1'b0;
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else if(w_enter) s_bvalid <= 1'b1;
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else if(b_retire) s_bvalid <= 1'b0;
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end
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assign s_rid = buf_id;
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assign s_bid = buf_id;
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assign s_bresp = 2'b0;
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assign s_rresp = 2'b0;
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//-------------------------------{dvi controller}begin----------------------------//
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wire write_reg_en[3:0];
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assign write_reg_en[0] = w_enter & (buf_addr[15:0]==16'h0);
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assign write_reg_en[1] = w_enter & (buf_addr[15:0]==16'h4);
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assign write_reg_en[2] = w_enter & (buf_addr[15:0]==16'h8);
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assign write_reg_en[3] = w_enter & (buf_addr[15:0]==16'hc);
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always @(posedge aclk) begin
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if(!aresetn) begin
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DVI_RECT_DIR <= 32'h0;
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end
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else if (write_reg_en[0]) begin
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DVI_RECT_DIR <= s_wdata;
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end
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end
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always @(posedge aclk) begin
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if(!aresetn) begin
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DVI_RECT_L_W <= 32'h0;
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end
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else if (write_reg_en[1]) begin
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DVI_RECT_L_W <= s_wdata;
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end
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end
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always @(posedge aclk) begin
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if(!aresetn) begin
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DVI_SQU_DIR <= 32'h0;
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end
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else if (write_reg_en[2]) begin
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DVI_SQU_DIR <= s_wdata;
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end
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end
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always @(posedge aclk) begin
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if(!aresetn) begin
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DVI_SQU_R <= 32'h0;
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end
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else if (write_reg_en[3]) begin
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DVI_SQU_R <= s_wdata;
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end
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end
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reg [WIDTH-1:0] hdata = 0; // Horizontal position counter
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reg [WIDTH-1:0] vdata = 0; // Vertical position counter
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wire hdata_in_range;
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wire vdata_in_range;
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wire hdata1_in_range;
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wire vdata1_in_range;
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always @(posedge aclk) begin
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if (hdata == (HMAX - 1)) // If horizontal counter reaches max
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hdata <= 0; // Reset horizontal counter
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else
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hdata <= hdata + 1; // Increment horizontal counter
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end
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// Vertical counter (vdata) logic
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always @(posedge aclk) begin
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if (hdata == (HMAX - 1)) begin
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if (vdata == (VMAX - 1)) // If vertical counter reaches max
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vdata <= 0; // Reset vertical counter
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else
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vdata <= vdata + 1; // Increment vertical counter
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end
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end
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// Horizontal sync signal generation (hsync)
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assign video_clk = aclk; // Example: using input clock as video clock
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assign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP;
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assign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP;
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assign data_enable = ((hdata < HSIZE) & (vdata < VSIZE));
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assign hdata_in_range = (hdata > (DVI_RECT_DIR[31:16]-DVI_RECT_L_W[31:16])) && (hdata < (DVI_RECT_DIR[31:16]+DVI_RECT_L_W[31:16]));
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// Check if vdata is in the range specified by DVI_RECT_L_W
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assign vdata_in_range = (vdata > DVI_RECT_DIR[15:0]) && (vdata <(DVI_RECT_DIR[15:0]+DVI_RECT_L_W[15:0]));
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assign hdata1_in_range = (hdata > (DVI_SQU_DIR[31:16]-DVI_SQU_R[31:16])) && (hdata < (DVI_SQU_DIR[31:16]+DVI_SQU_R[31:16]));
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// Check if vdata is in the range specified by DVI_RECT_L_W
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assign vdata1_in_range = (vdata > (DVI_SQU_DIR[15:0]-DVI_SQU_R[15:0])) && (vdata <(DVI_SQU_DIR[15:0]+DVI_SQU_R[15:0]));
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// Set video output colors based on conditions
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assign video_red = ((hdata_in_range && vdata_in_range)||(hdata1_in_range && vdata1_in_range)) ? 3'b111 : 3'b0;
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assign video_green = 3'b0;
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assign video_blue = 2'b0;
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//--------------------------------{dvi controller}end-----------------------------//
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endmodule |