422 lines
13 KiB
Verilog
422 lines
13 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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`define CONFREG_INT_ADDR 16'hf000 //1f20_f000
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`define TIMER_ADDR 16'hf100 //1f20_f100
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`define DIGITAL_ADDR 16'hf200 //1f20_f200
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`define LED_ADDR 16'hf300 //1f20_f300
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`define SWITCH_ADDR 16'hf400 //1f20_f400
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`define SIMU_FLAG_ADDR 16'hf500 //1f20_f500
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module confreg #(
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parameter SIMULATION=1'b0
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)
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(
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input aclk,
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input aresetn,
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input cpu_clk,
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input cpu_resetn,
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input [4 :0] s_awid,
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input [31:0] s_awaddr,
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input [7 :0] s_awlen,
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input [2 :0] s_awsize,
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input [1 :0] s_awburst,
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input s_awlock,
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input [3 :0] s_awcache,
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input [2 :0] s_awprot,
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input s_awvalid,
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output s_awready,
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input [4 :0] s_wid,
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input [31:0] s_wdata,
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input [3 :0] s_wstrb,
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input s_wlast,
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input s_wvalid,
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output reg s_wready,
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output [4 :0] s_bid,
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output [1 :0] s_bresp,
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output reg s_bvalid,
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input s_bready,
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input [4 :0] s_arid,
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input [31:0] s_araddr,
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input [7 :0] s_arlen,
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input [2 :0] s_arsize,
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input [1 :0] s_arburst,
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input s_arlock,
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input [3 :0] s_arcache,
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input [2 :0] s_arprot,
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input s_arvalid,
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output s_arready,
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output [4 :0] s_rid,
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output reg [31:0] s_rdata,
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output [1 :0] s_rresp,
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output reg s_rlast,
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output reg s_rvalid,
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input s_rready,
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output [15:0] led,
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output [7:0] dpy0,
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output [7:0] dpy1,
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input [31:0] switch,
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input [3 :0] touch_btn,
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input uart0_int,
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input dma_finish,
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input fft_finish,
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output confreg_int
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);
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wire [3:0] touch_btn_data;//按键中断信号，上升沿触发
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reg [31:0] led_data;
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wire [31:0] switch_data;
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reg [31:0] simu_flag;
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reg [31:0] confreg_int_en,confreg_int_edge,confreg_int_pol,confreg_int_clr,confreg_int_set;
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wire [31:0] confreg_int_state;
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reg [31:0] sys_timer,sys_timer_cmp;
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reg sys_timer_en;
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reg timer_int;//定时器中断信号，高电平触发
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reg [31:0] digital_ctrl;
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reg [31:0] digital_data;
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reg busy,write,R_or_W;
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wire ar_enter = s_arvalid & s_arready;
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wire r_retire = s_rvalid & s_rready & s_rlast;
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wire aw_enter = s_awvalid & s_awready;
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wire w_enter = s_wvalid & s_wready & s_wlast;
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wire b_retire = s_bvalid & s_bready;
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assign s_arready = ~busy & (!R_or_W| !s_awvalid);
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assign s_awready = ~busy & ( R_or_W| !s_arvalid);
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always@(posedge aclk)
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if(~aresetn) busy <= 1'b0;
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else if(ar_enter|aw_enter) busy <= 1'b1;
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else if(r_retire|b_retire) busy <= 1'b0;
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reg [4 :0] buf_id;
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reg [31:0] buf_addr;
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reg [7 :0] buf_len;
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reg [2 :0] buf_size;
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reg [1 :0] buf_burst;
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reg buf_lock;
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reg [3 :0] buf_cache;
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reg [2 :0] buf_prot;
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always@(posedge aclk)
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if(~aresetn) begin
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R_or_W <= 1'b0;
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buf_id <= 'b0;
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buf_addr <= 'b0;
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buf_len <= 'b0;
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buf_size <= 'b0;
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buf_burst <= 'b0;
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buf_lock <= 'b0;
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buf_cache <= 'b0;
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buf_prot <= 'b0;
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end
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else
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if(ar_enter | aw_enter) begin
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R_or_W <= ar_enter;
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buf_id <= ar_enter ? s_arid : s_awid ;
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buf_addr <= ar_enter ? s_araddr : s_awaddr ;
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buf_len <= ar_enter ? s_arlen : s_awlen ;
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buf_size <= ar_enter ? s_arsize : s_awsize ;
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buf_burst <= ar_enter ? s_arburst: s_awburst;
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buf_lock <= ar_enter ? s_arlock : s_awlock ;
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buf_cache <= ar_enter ? s_arcache: s_awcache;
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buf_prot <= ar_enter ? s_arprot : s_awprot ;
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end
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always@(posedge aclk)
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if(~aresetn) write <= 1'b0;
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else if(aw_enter) write <= 1'b1;
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else if(ar_enter) write <= 1'b0;
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always@(posedge aclk)
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if(~aresetn) s_wready <= 1'b0;
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else if(aw_enter) s_wready <= 1'b1;
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else if(w_enter & s_wlast) s_wready <= 1'b0;
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wire [31:0] rdata_d = buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h0) ? confreg_int_en :
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buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h4) ? confreg_int_edge :
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buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h8) ? confreg_int_pol :
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buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'hc) ? confreg_int_clr :
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buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h10) ? confreg_int_set :
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buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h14) ? confreg_int_state :
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buf_addr[15:0] == (`TIMER_ADDR + 16'h0) ? sys_timer :
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buf_addr[15:0] == (`TIMER_ADDR + 16'h4) ? sys_timer_cmp :
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buf_addr[15:0] == (`TIMER_ADDR + 16'h8) ? sys_timer_en :
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buf_addr[15:0] == (`DIGITAL_ADDR + 16'h0) ? digital_ctrl :
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buf_addr[15:0] == (`DIGITAL_ADDR + 16'h4) ? digital_data :
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buf_addr[15:0] == `LED_ADDR ? led_data :
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buf_addr[15:0] == `SWITCH_ADDR ? switch_data :
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buf_addr[15:0] == `SIMU_FLAG_ADDR ? simu_flag :
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32'd0;
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always@(posedge aclk)
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if(~aresetn) begin
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s_rdata <= 'b0;
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s_rvalid <= 1'b0;
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s_rlast <= 1'b0;
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end
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else if(busy & !write & !r_retire)
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begin
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s_rdata <= rdata_d;
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s_rvalid <= 1'b1;
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s_rlast <= 1'b1;
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end
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else if(r_retire)
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begin
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s_rvalid <= 1'b0;
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end
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always@(posedge aclk)
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if(~aresetn) s_bvalid <= 1'b0;
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else if(w_enter) s_bvalid <= 1'b1;
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else if(b_retire) s_bvalid <= 1'b0;
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assign s_rid = buf_id;
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assign s_bid = buf_id;
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assign s_bresp = 2'b0;
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assign s_rresp = 2'b0;
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//-------------------------------{touch_btn}begin----------------------------//
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assign touch_btn_data = touch_btn;
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// genvar i;
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// generate for(i=0;i<4;i=i+1) begin: generate_btn_debounce
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// key_debounce u_key_debounce(
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// .sys_clk(aclk),
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// .key(touch_btn[i]),
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// .key_out(touch_btn_data[i])
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// );
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// end
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// endgenerate
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//--------------------------------{touch_btn}end-----------------------------//
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//-------------------------------{timer}begin----------------------------//
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wire write_timer_cmp = w_enter & (buf_addr[15:0]==`TIMER_ADDR+16'h4);
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wire write_timer_en = w_enter & (buf_addr[15:0]==`TIMER_ADDR+16'h8);
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always @(posedge aclk) begin
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if(!aresetn) begin
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sys_timer_cmp <= 32'h0;
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end
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else if (write_timer_cmp) begin
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sys_timer_cmp <= s_wdata;
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end
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end
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always @(posedge aclk) begin
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if(!aresetn) begin
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sys_timer_en <= 1'b0;
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end
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else if (write_timer_en) begin
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sys_timer_en <= s_wdata[0];
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end
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end
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always @(posedge aclk or negedge aresetn) begin
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if (!aresetn) begin
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sys_timer <= 32'h0;
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timer_int <= 1'b0;
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end
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else if (sys_timer_en) begin
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if (sys_timer >= sys_timer_cmp - 1) begin
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sys_timer <= 32'h0;
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timer_int <= 1'b1;
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end else begin
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sys_timer <= sys_timer + 1'b1;
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end
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end
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else begin
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sys_timer <= 32'h0;
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timer_int <= 1'b0;
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end
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end
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//--------------------------------{timer}end-----------------------------//
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//--------------------------------{led}begin-----------------------------//
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//led display
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//led_data[31:0]
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wire write_led = w_enter & (buf_addr[15:0]==`LED_ADDR);
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assign led = led_data[15:0];
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always @(posedge aclk)
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begin
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if(!aresetn)
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begin
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led_data <= 32'h0;
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end
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else if(write_led)
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begin
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led_data <= s_wdata[31:0];
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end
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end
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//---------------------------------{led}end------------------------------//
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//-------------------------------{switch}begin---------------------------//
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//switch data
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//switch_data[31:0]
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assign switch_data = switch;
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//--------------------------------{switch}end----------------------------//
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//---------------------------{digital number}begin-----------------------//
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wire write_digital_ctrl = w_enter & (buf_addr[15:0]==`DIGITAL_ADDR + 16'h0);
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wire write_digital_data = w_enter & (buf_addr[15:0]==`DIGITAL_ADDR + 16'h4);
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always @(posedge aclk) begin
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if(!aresetn) begin
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digital_ctrl <= 32'd0;
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end
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else if (write_digital_ctrl) begin
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digital_ctrl <= s_wdata;
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end
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end
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always @(posedge aclk) begin
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if(!aresetn) begin
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digital_data <= 32'd0;
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end
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else if (write_digital_data) begin
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digital_data <= s_wdata;
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end
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end
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wire [31:0] digital_data_in = digital_data;
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digitaltube_controller u_digitaltube_controller (
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.control_reg ( digital_ctrl ),
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.clk ( aclk ),
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.rst_n ( aresetn ),
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.dpy0 ( dpy0 ),
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.dpy1 ( dpy1 ),
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.data_reg ( digital_data_in )
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);
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//----------------------------{digital number}end------------------------//
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//--------------------------{simulation flag}begin-----------------------//
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always @(posedge aclk)
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begin
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if(!aresetn) begin
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simu_flag <= {32{SIMULATION}};
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end
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else begin
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simu_flag <= {32{SIMULATION}};
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end
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end
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//---------------------------{simulation flag}end------------------------//
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//-------------------------------{int_ctrl}begin----------------------------//
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//add your code
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wire [31:0] int_in;
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wire [31:0] int_out;
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wire write_int_en = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h0));
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wire write_int_edge = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h4));
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wire write_int_pol = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h8));
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wire write_int_clr = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'hc));
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wire write_int_set = w_enter & (buf_addr[15:0] == (`CONFREG_INT_ADDR + 16'h10));
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always @(posedge aclk) begin
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if (!aresetn) begin
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confreg_int_en <= 32'h0;
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confreg_int_edge <= 32'h0;
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confreg_int_pol <= 32'h0;
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end else begin
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if (write_int_en) confreg_int_en <= s_wdata;
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if (write_int_edge) confreg_int_edge <= s_wdata;
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if (write_int_pol) confreg_int_pol <= s_wdata;
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end
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end
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always @(posedge aclk) begin
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if (!aresetn) begin
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confreg_int_clr <= 32'h0;
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confreg_int_set <= 32'h0;
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end else begin
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confreg_int_clr <= write_int_clr ? s_wdata : 32'h0;
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confreg_int_set <= write_int_set ? s_wdata : 32'h0;
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end
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end
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assign int_in = {24'b0, dma_finish, fft_finish, uart0_int, timer_int, touch_btn_data};
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int_ctrl u_int_ctrl (
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.clk (aclk),
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.resetn (aresetn),
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.int_en (confreg_int_en),
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.int_edge (confreg_int_edge),
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.int_pol (confreg_int_pol),
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.int_in (int_in),
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.int_clr (confreg_int_clr),
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.int_set (confreg_int_set),
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.int_out (int_out)
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);
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assign confreg_int_state = int_out;
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// int_out 进行或操作，再经过延迟打拍处理
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reg int_out_or_q1;
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reg int_out_or_q2;
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always @(posedge aclk) begin
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if (!aresetn) begin
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int_out_or_q1 <= 1'b0;
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int_out_or_q2 <= 1'b0;
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end else begin
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int_out_or_q1 <= |int_out;
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int_out_or_q2 <= int_out_or_q1;
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end
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end
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assign confreg_int = int_out_or_q2;
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//--------------------------------{int_ctrl}end-----------------------------//
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endmodule
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