40 lines
1.2 KiB
Verilog
40 lines
1.2 KiB
Verilog
module key_debounce(
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input sys_clk, //外部时钟20M
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input key, //外部按键输入
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output wire key_out //按键消抖后的数据
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);
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//reg define
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reg [31:0] delay_cnt; //延时计数
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reg key_reg;
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reg key_value = 1'b1;
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//*****************************************************
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//** main code
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//*****************************************************
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always @(posedge sys_clk ) begin
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key_reg <= key;
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if(key_reg != key) //一旦检测到按键状态发生变化(有按键被按下或释放)
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delay_cnt <= 32'd400000; //给延时计数器重新装载初始值（计数时间为 20ms）
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else if(key_reg == key) begin //在按键状态稳定时，计数器递减，开始 20ms 倒计时
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if(delay_cnt > 32'd0)
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delay_cnt <= delay_cnt - 1'b1;
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else
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delay_cnt <= delay_cnt;
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end
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end
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always @(posedge sys_clk ) begin
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if(delay_cnt == 32'd1) begin //当计数器递减到 1 时，说明按键稳定状态维持了 20ms
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key_value <= key; //并寄存此时按键的值
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end
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else begin
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key_value <= key_out;
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end
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end
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assign key_out = key & key_value ;
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endmodule |