383 lines
12 KiB
Verilog
383 lines
12 KiB
Verilog
`define FFT_CSR_ADDR 16'hf000
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`define FFT_IN_RE_BASE 16'h1000
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`define FFT_IN_IM_BASE 16'h2000
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`define FFT_OUT_RE_BASE 16'h3000
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`define FFT_OUT_IM_BASE 16'h4000
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module fft_controller #(
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parameter FFT_LEN = 1024, // FFT处理长度
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parameter BRAM_RD_LATENCY = 2 // 适配 BRAM 的读延迟 (通常 Block RAM 开启输出寄存器为 2)
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)(
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input aclk,
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input aresetn,
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// AXI Lite / AXI4 Wrapper ports
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input [4 :0] s_awid,
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input [31:0] s_awaddr,
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input [7 :0] s_awlen,
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input [2 :0] s_awsize,
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input [1 :0] s_awburst,
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input s_awlock,
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input [3 :0] s_awcache,
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input [2 :0] s_awprot,
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input s_awvalid,
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output reg s_awready,
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input [4 :0] s_wid,
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input [31:0] s_wdata,
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input [3 :0] s_wstrb,
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input s_wlast,
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input s_wvalid,
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output reg s_wready,
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output [4 :0] s_bid,
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output [1 :0] s_bresp,
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output reg s_bvalid,
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input s_bready,
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input [4 :0] s_arid,
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input [31:0] s_araddr,
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input [7 :0] s_arlen,
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input [2 :0] s_arsize,
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input [1 :0] s_arburst,
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input s_arlock,
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input [3 :0] s_arcache,
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input [2 :0] s_arprot,
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input s_arvalid,
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output reg s_arready,
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output [4 :0] s_rid,
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output reg [31:0] s_rdata,
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output [1 :0] s_rresp,
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output reg s_rlast,
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output reg s_rvalid,
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input s_rready,
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output fft_finish
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);
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// AXI Burst 内部寄存器
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reg [31:0] aw_addr_reg;
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reg [1 :0] aw_burst_reg;
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reg [4 :0] aw_id_reg;
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reg [31:0] ar_addr_reg;
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reg [7 :0] ar_len_reg;
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reg [1 :0] ar_burst_reg;
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reg [4 :0] ar_id_reg;
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reg [7 :0] ar_cnt;
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// 写通道状态机 (AW, W, B)
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localparam W_IDLE = 2'd0;
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localparam W_DATA = 2'd1;
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localparam W_RESP = 2'd2;
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reg [1:0] w_state;
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always @(posedge aclk) begin
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if (~aresetn) begin
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w_state <= W_IDLE;
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s_awready <= 1'b1;
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s_wready <= 1'b0;
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s_bvalid <= 1'b0;
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aw_addr_reg <= 32'h0;
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aw_burst_reg <= 2'h0;
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aw_id_reg <= 5'h0;
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end else begin
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case (w_state)
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W_IDLE: begin
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s_awready <= 1'b1;
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if (s_awvalid && s_awready) begin
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s_awready <= 1'b0;
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s_wready <= 1'b1;
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aw_addr_reg <= s_awaddr;
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aw_burst_reg <= s_awburst;
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aw_id_reg <= s_awid;
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w_state <= W_DATA;
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end
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end
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W_DATA: begin
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// 接收到有效写数据
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if (s_wvalid && s_wready) begin
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// INCR 模式下地址递增
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if (aw_burst_reg == 2'b01) begin
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aw_addr_reg <= aw_addr_reg + 4;
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end
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// 若是最后一拍，跳转到发送响应
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if (s_wlast) begin
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s_wready <= 1'b0;
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s_bvalid <= 1'b1;
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w_state <= W_RESP;
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end
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end
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end
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W_RESP: begin
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if (s_bvalid && s_bready) begin
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s_bvalid <= 1'b0;
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s_awready <= 1'b1; // 准备接收下一次写请求
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w_state <= W_IDLE;
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end
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end
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default: w_state <= W_IDLE;
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endcase
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end
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end
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// 产生有效的写动作脉冲，用于触发 BRAM 写使能
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wire w_active = (w_state == W_DATA) && s_wvalid && s_wready;
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assign s_bid = aw_id_reg;
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assign s_bresp = 2'b00;
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// 读通道状态机(AR, R)
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localparam R_IDLE = 2'd0;
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localparam R_WAIT = 2'd1;
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localparam R_DATA = 2'd2;
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reg [1:0] r_state;
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reg [3:0] r_wait_cnt;
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always @(posedge aclk) begin
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if (~aresetn) begin
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r_state <= R_IDLE;
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s_arready <= 1'b1;
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s_rvalid <= 1'b0;
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s_rlast <= 1'b0;
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ar_addr_reg <= 32'h0;
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ar_len_reg <= 8'h0;
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ar_burst_reg <= 2'h0;
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ar_id_reg <= 5'h0;
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ar_cnt <= 8'h0;
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r_wait_cnt <= 4'h0;
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end else begin
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case (r_state)
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R_IDLE: begin
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s_arready <= 1'b1;
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if (s_arvalid && s_arready) begin
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s_arready <= 1'b0;
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ar_addr_reg <= s_araddr;
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ar_len_reg <= s_arlen;
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ar_burst_reg <= s_arburst;
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ar_id_reg <= s_arid;
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ar_cnt <= 8'h0;
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r_wait_cnt <= BRAM_RD_LATENCY;
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r_state <= R_WAIT; // 进入等待以拉取第一笔 BRAM 数据
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end
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end
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R_WAIT: begin
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// 等待 BRAM 固定潜伏期结束
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if (r_wait_cnt <= 1) begin
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s_rvalid <= 1'b1;
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s_rlast <= (ar_cnt == ar_len_reg);
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r_state <= R_DATA;
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r_wait_cnt <= 4'h0;
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end else begin
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r_wait_cnt <= r_wait_cnt - 1;
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end
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end
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R_DATA: begin
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// 数据被总线成功读取
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if (s_rvalid && s_rready) begin
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if (ar_cnt == ar_len_reg) begin
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// Burst 结束
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s_rvalid <= 1'b0;
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s_rlast <= 1'b0;
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s_arready <= 1'b1;
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r_state <= R_IDLE;
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end else begin
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// 准备读取下一拍数据
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ar_cnt <= ar_cnt + 1;
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// INCR 模式下地址递增
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if (ar_burst_reg == 2'b01) begin
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ar_addr_reg <= ar_addr_reg + 4;
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end
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s_rvalid <= 1'b0;
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s_rlast <= 1'b0;
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r_wait_cnt <= BRAM_RD_LATENCY;
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r_state <= R_WAIT; // 再次进入等待状态
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end
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end
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end
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default: r_state <= R_IDLE;
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endcase
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end
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end
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assign s_rid = ar_id_reg;
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assign s_rresp = 2'b00;
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// 地址译码
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wire hit_in_re = (aw_addr_reg[15:12] == 4'h1);
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wire hit_in_im = (aw_addr_reg[15:12] == 4'h2);
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wire hit_out_re = (ar_addr_reg[15:12] == 4'h3);
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wire hit_out_im = (ar_addr_reg[15:12] == 4'h4);
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// 寄存器控制
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reg [3:0] fft_ctrl;
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reg [3:0] fft_status;
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wire [31:0] fft_csr = {24'h0, fft_ctrl, fft_status};
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// 只有发生有效的写握手且地址对应 CSR 时，才写入控制寄存器
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wire write_fft_csr = w_active && (aw_addr_reg[15:0] == `FFT_CSR_ADDR);
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// 状态机
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localparam IDLE = 2'd0;
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localparam LOAD = 2'd1;
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localparam WAIT_OUT = 2'd2;
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localparam DONE = 2'd3;
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reg [1:0] state, next_state;
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reg [10:0] in_cnt;
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reg [10:0] out_cnt;
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wire do_en;
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wire [31:0] do_re;
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wire [31:0] do_im;
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always @(posedge aclk) begin
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if (~aresetn) state <= IDLE;
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else state <= next_state;
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end
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always @(*) begin
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case (state)
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IDLE: if (fft_ctrl[0]) next_state = LOAD; else next_state = IDLE;
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LOAD: if (in_cnt == FFT_LEN - 1) next_state = WAIT_OUT; else next_state = LOAD;
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WAIT_OUT: if (do_en && out_cnt == FFT_LEN - 1) next_state = DONE; else next_state = WAIT_OUT;
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DONE: next_state = IDLE;
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default: next_state = IDLE;
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endcase
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end
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always @(posedge aclk) begin
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if (~aresetn) begin
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in_cnt <= 0;
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out_cnt <= 0;
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end else if (state == IDLE) begin
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in_cnt <= 0;
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out_cnt <= 0;
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end else begin
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if (state == LOAD) in_cnt <= in_cnt + 1;
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if (do_en) out_cnt <= out_cnt + 1;
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end
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end
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// 更新寄存器与状态
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always @(posedge aclk) begin
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if (~aresetn) begin
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fft_ctrl <= 4'h0;
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fft_status <= 4'h0;
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end else begin
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if (write_fft_csr) begin
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fft_ctrl <= s_wdata[7:4];
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end else if (state != IDLE) begin
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fft_ctrl[0] <= 1'b0;
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end
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fft_status[0] <= (state != IDLE && state != DONE);
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if (write_fft_csr && s_wdata[4]) begin
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fft_status[1] <= 1'b0;
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end else if (state == DONE) begin
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fft_status[1] <= 1'b1;
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end
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end
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end
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assign fft_finish = fft_status[1];
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// BRAM 接口连线
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wire [31:0] in_re_dout;
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wire [31:0] in_im_dout;
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wire [31:0] out_re_dout;
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wire [31:0] out_im_dout;
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bram0 u_in0(
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.clka (aclk),
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.ena (w_active && hit_in_re), // 由 burst写逻辑产生
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.wea (1'b1),
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.addra (aw_addr_reg[11:2]), // 取当前递增的突发写地址
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.dina (s_wdata),
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.clkb (aclk),
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.enb (state == LOAD),
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.addrb (in_cnt[9:0]),
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.doutb (in_re_dout)
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);
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bram0 u_in1(
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.clka (aclk),
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.ena (w_active && hit_in_im),
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.wea (1'b1),
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.addra (aw_addr_reg[11:2]),
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.dina (s_wdata),
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.clkb (aclk),
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.enb (state == LOAD),
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.addrb (in_cnt[9:0]),
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.doutb (in_im_dout)
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);
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// 对于输出 BRAM，采用原先的位反转（Bit-reverse）读取逻辑
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wire [9:0] b_rd_addr = ar_addr_reg[11:2];
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wire [9:0] bit_reversed_index = {
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b_rd_addr[0], b_rd_addr[1], b_rd_addr[2], b_rd_addr[3], b_rd_addr[4],
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b_rd_addr[5], b_rd_addr[6], b_rd_addr[7], b_rd_addr[8], b_rd_addr[9]
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};
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bram0 u_out0(
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.clka (aclk),
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.ena (do_en),
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.wea (1'b1),
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.addra (out_cnt[9:0]),
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.dina (do_re),
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.clkb (aclk),
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.enb (r_state != R_IDLE), // 当处于读突发事务时始终使能 BRAM
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.addrb (bit_reversed_index),
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.doutb (out_re_dout)
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);
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bram0 u_out1(
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.clka (aclk),
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.ena (do_en),
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.wea (1'b1),
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.addra (out_cnt[9:0]),
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.dina (do_im),
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.clkb (aclk),
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.enb (r_state != R_IDLE),
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.addrb (bit_reversed_index),
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.doutb (out_im_dout)
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);
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// 支持 1 到 N 拍的读延迟，让 di_en 严格对齐 BRAM 的吐出数据
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reg [3:0] di_en_shift;
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always @(posedge aclk) begin
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if (~aresetn) di_en_shift <= 0;
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else di_en_shift <= {di_en_shift[2:0], (state == LOAD)};
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end
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wire di_en_r = (BRAM_RD_LATENCY == 1) ? di_en_shift[0] :
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(BRAM_RD_LATENCY == 2) ? di_en_shift[1] :
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(BRAM_RD_LATENCY == 3) ? di_en_shift[2] : di_en_shift[3];
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FFT #(
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.WIDTH(32)
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) u_FFT (
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.clock (aclk),
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.reset (~aresetn),
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.di_en (di_en_r),
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.di_re (in_re_dout),
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.di_im (in_im_dout),
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.do_en (do_en),
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.do_re (do_re),
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.do_im (do_im)
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);
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// 读取返回数据选择
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wire [31:0] rdata_d =
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(ar_addr_reg[15:0] == `FFT_CSR_ADDR) ? fft_csr :
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hit_out_re ? out_re_dout :
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hit_out_im ? out_im_dout :
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32'h0;
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always @(*) begin
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s_rdata = rdata_d;
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end
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endmodule |