183 lines
3.9 KiB
ArmAsm
183 lines
3.9 KiB
ArmAsm
#include "regdef.h"
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#include "uart_print.h"
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#include "handler.h"
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.extern UART_BASE
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.section .init
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.globl _start
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.type _start,@function
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_start:
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##init regs
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addi.w $r1,zero,0x0; addi.w $r2,zero,0x0; addi.w $r3,zero,0x0; addi.w $r4,zero,0x0;
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addi.w $r5,zero,0x0; addi.w $r6,zero,0x0; addi.w $r7,zero,0x0; addi.w $r8,zero,0x0;
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addi.w $r9,zero,0x0; addi.w $r10,zero,0x0; addi.w $r11,zero,0x0; addi.w $r12,zero,0x0;
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addi.w $r13,zero,0x0; addi.w $r14,zero,0x0; addi.w $r15,zero,0x0; addi.w $r16,zero,0x0;
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addi.w $r17,zero,0x0; addi.w $r18,zero,0x0; addi.w $r19,zero,0x0; addi.w $r20,zero,0x0;
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addi.w $r21,zero,0x0; addi.w $r22,zero,0x0; addi.w $r23,zero,0x0; addi.w $r24,zero,0x0;
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addi.w $r25,zero,0x0; addi.w $r26,zero,0x0; addi.w $r27,zero,0x0; addi.w $r28,zero,0x0;
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addi.w $r29,zero,0x0; addi.w $r30,zero,0x0; addi.w $r31,zero,0x0;
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#if has_cache==1
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# invalid the old inst in icache and old data in dcache by index
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li.w t0,0x0
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#li.w t2,0x100
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li.w t2, cache_index_depth
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1:
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#slli.w t1, t0, 0x4
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slli.w t1, t0, cache_offset_width
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#if cache_way==1
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cacop 0x00, t1, 0x0
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cacop 0x01, t1, 0x0
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#elif cache_way==2
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cacop 0x00, t1, 0x0
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cacop 0x00, t1, 0x1
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cacop 0x01, t1, 0x0
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cacop 0x01, t1, 0x1
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#elif cache_way==4
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cacop 0x00, t1, 0x0
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cacop 0x00, t1, 0x1
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cacop 0x00, t1, 0x2
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cacop 0x00, t1, 0x3
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cacop 0x01, t1, 0x0
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cacop 0x01, t1, 0x1
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cacop 0x01, t1, 0x2
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cacop 0x01, t1, 0x3
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#endif
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addi.w t0, t0, 0x1
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bne t0, t2, 1b
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#else
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/* disable cache */
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li.w $r12,0x1
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csrwr $r12,0x101
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#endif
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/* open da mode */
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li.w $r12,0x8
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li.w $r13,0x18
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csrxchg $r12,$r13,0x0
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/* init dmw */
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csrwr $r0,0x180
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csrwr $r0,0x181
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li.w $r12,0x09
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csrwr $r12,0x180
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li.w $r12,0xa0000009
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csrwr $r12,0x181
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/* open pg mode */
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li.w $r12,0x10
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li.w $r13,0x18
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csrxchg $r12,$r13,0x0
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/* load data section */
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la.local t0, _data_lma
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la.local t1, _data
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la.local t2, _edata
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bgeu t1, t2, 2f
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1:
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ld.w t3, t0, 0
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st.w t3, t1, 0
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addi.w t0, t0, 4
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addi.w t1, t1, 4
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bltu t1, t2, 1b
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2:
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/* clear bss section */
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la.local t0, __bss_start
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la.local t1, _end
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bgeu t0, t1, 2f
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1:
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st.w $r0, t0, 0
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addi.w t0, t0, 4
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bltu t0, t1, 1b
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2:
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/* enable cache */
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#if has_cache==1
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li.w $r12,0x19
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csrwr $r12,0x180
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#else
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#endif
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/* init UART */
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la.local t0, UART_BASE
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ld.w t1, t0, 0
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#WRITE(li.wne,OFS_FIFO,FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_0);
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li.w t2, 0x07
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st.b t2, t1, 2
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#WRITE(li.wne,OFS_LINE_CONTROL, 0x80);
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li.w t2, 0x80
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st.b t2, t1, 3
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#WRITE(li.wne,OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
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li.w t2, 0x00
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st.b t2, t1, 1
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#WRITE(li.wne,OFS_DIVISOR_LSB, divisor & 0xff);
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li.w t3, 0xbf20f500
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ld.w t3, t3, 0
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li.w t2, 0x1b
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beq zero, t3, 1f
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li.w t2, 0x1
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1:
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st.b t2, t1, 0
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#WRITE(li.wne,OFS_DATA_FORMAT, data | parity | stop);
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li.w t2, 0x3
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st.b t2, t1, 3
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#WRITE(li.wne,OFS_MODEM_CONTROL,0);
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li.w t2, 0x0
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st.b t2, t1, 4
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/* init exception */
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#ifdef RTThread
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la.local t0, rtthread_irq_entry
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#else
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la.local t0, trap_handler
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#endif
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csrwr t0, csr_eentry
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#clear int
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li.w t1, 0x1
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csrwr t1, csr_ticlr
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#enable int
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li.w t1, 0x4
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#ifdef RTThread
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csrxchg zero, t1, csr_crmd
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#else
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csrxchg t1, t1, csr_crmd
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#endif
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csrwr zero, csr_prmd
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li.w t1, 0x1fff
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csrwr zero, csr_ecfg
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csrwr t1, csr_ecfg
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la.local sp, _stack
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/* argc = argv = 0 */
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li.w a0, 0
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li.w a1, 0
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#ifdef RTThread
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bl entry
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#else
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bl main
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#endif
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/*tail exit*/
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bl _myexit
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1:
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b 1b
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.globl _myexit
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.org 0x200
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_myexit:
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1:
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b 1b
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