85 lines
2.2 KiB
Verilog
85 lines
2.2 KiB
Verilog
`include "config.h"
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module data_bank_sram (
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input [ 7:0] addra ,
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input clka ,
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input [31:0] dina ,
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output [31:0] douta ,
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input ena ,
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input [ 3:0] wea
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);
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`ifdef USE_CACHE
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localparam V_STYLE = "block";
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localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
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(V_STYLE == "distributed") ? "select_ram" :
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"block_ram";
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(*ram_style = V_STYLE*) reg [31:0] mem_reg [255:0]/*synthesis syn_ramstyle=P_STYLE*/;
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reg [31:0] output_buffer;
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always @(posedge clka) begin
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if (ena) begin
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if (wea) begin
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if (wea[0]) begin
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mem_reg[addra][ 7: 0] <= dina[ 7: 0];
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end
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if (wea[1]) begin
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mem_reg[addra][15: 8] <= dina[15: 8];
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end
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if (wea[2]) begin
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mem_reg[addra][23:16] <= dina[23:16];
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end
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if (wea[3]) begin
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mem_reg[addra][31:24] <= dina[31:24];
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end
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end
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else begin
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output_buffer <= mem_reg[addra];
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end
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end
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end
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assign douta = output_buffer;
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`else
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assign douta = 32'h0;
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`endif
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endmodule
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module tagv_sram (
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input [ 7:0] addra ,
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input clka ,
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input [20:0] dina ,
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output [20:0] douta ,
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input ena ,
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input wea
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);
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`ifdef USE_CACHE
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localparam V_STYLE = "block";
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localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
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(V_STYLE == "distributed") ? "select_ram" :
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"block_ram";
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(*ram_style = V_STYLE*) reg [20:0] mem_reg [255:0]/*synthesis syn_ramstyle=P_STYLE*/;
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reg [20:0] output_buffer;
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always @(posedge clka) begin
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if (ena) begin
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if (wea) begin
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mem_reg[addra] <= dina;
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end
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else begin
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output_buffer <= mem_reg[addra];
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end
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end
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end
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assign douta = output_buffer;
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`else
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assign douta = 21'h0;
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`endif
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endmodule |