fallensigh/ciciec2026_loongson
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

feat(top): integrate CDMA and FFT modules

Browse Source
This commit is contained in:
FallenSigh
2026-04-12 22:27:09 +08:00
parent 5aa5ba8e45
commit 3d4096f94e
1 changed files with 630 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

693
rtl/soc_top.v
View File

@@ -359,32 +359,6 @@ wire [1 :0] dma_m_bresp ;
wire dma_m_bvalid ;
wire dma_m_bready ;
assign dma_m_arid = 4'b0 ;
assign dma_m_araddr = 32'h0;
assign dma_m_arlen = 8'b0 ;
assign dma_m_arsize = 3'b0 ;
assign dma_m_arburst = 2'b0;
assign dma_m_arlock = 1'b0;
assign dma_m_arcache = 4'b0;
assign dma_m_arprot = 3'b0;
assign dma_m_arvalid = 1'b0;
assign dma_m_rready = 1'b1;
assign dma_m_awid = 4'b0;
assign dma_m_awaddr = 32'b0;
assign dma_m_awlen = 8'b0;
assign dma_m_awsize = 3'b0;
assign dma_m_awburst = 2'b0;
assign dma_m_awlock = 1'b0;
assign dma_m_awcache = 4'b0;
assign dma_m_awprot = 3'b0;
assign dma_m_awvalid = 1'b1;
assign dma_m_wid = 4'b0;
assign dma_m_wdata = 32'b0;
assign dma_m_wstrb = 4'b0;
assign dma_m_wlast = 1'b0;
assign dma_m_wvalid = 1'b0;
assign dma_m_bready = 1'b1;
wire [4 :0] dma_s_arid ;
wire [31:0] dma_s_araddr ;
wire [7 :0] dma_s_arlen ;
@@ -422,18 +396,6 @@ wire dma_s_bvalid ;
wire dma_s_bready ;
wire dma_finish ;
assign dma_s_arready = 1'b1;
assign dma_s_rid = 5'b0;
assign dma_s_rdata = 32'b0;
assign dma_s_rresp = 2'b0;
assign dma_s_rlast = 1'b0;
assign dma_s_rvalid = 1'b0;
assign dma_s_awready = 1'b1;
assign dma_s_wready = 1'b1;
assign dma_s_bid = 5'b0;
assign dma_s_bresp = 2'b0;
assign dma_s_bvalid = 1'b0;
// reserved
wire [4 :0] axiOut_1_arid ;
wire [31:0] axiOut_1_araddr ;
@@ -523,18 +485,6 @@ wire [1 :0] dvi_bresp ;
wire dvi_bvalid ;
wire dvi_bready ;
assign dvi_arready = 1'b1;
assign dvi_rid = 5'b0;
assign dvi_rdata = 32'b0;
assign dvi_rresp = 2'b0;
assign dvi_rlast = 1'b0;
assign dvi_rvalid = 1'b0;
assign dvi_awready = 1'b1;
assign dvi_wready = 1'b1;
assign dvi_bid = 5'b0;
assign dvi_bresp = 2'b0;
assign dvi_bvalid = 1'b0;
//axi confreg
wire [4 :0] confreg_arid ;
wire [31:0] confreg_araddr ;
@@ -612,18 +562,6 @@ wire fft_bvalid ;
wire fft_bready ;
wire fft_finish ;
assign fft_arready = 1'b1;
assign fft_rid = 5'b0;
assign fft_rdata = 32'b0;
assign fft_rresp = 2'b0;
assign fft_rlast = 1'b0;
assign fft_rvalid = 1'b0;
assign fft_awready = 1'b1;
assign fft_wready = 1'b1;
assign fft_bid = 5'b0;
assign fft_bresp = 2'b0;
assign fft_bvalid = 1'b0;
//slave 7
wire [4 :0] axiOut_7_arid ;
wire [31:0] axiOut_7_araddr ;
@@ -1105,5 +1043,634 @@ AxiCrossbar_2x8 u_AxiCrossbar_2x8 (
// add your code
endmodule
core_top u_cpu(
.intrpt ({7'b0, confreg_int}), //high active
.aclk (cpu_clk ),
.aresetn (cpu_resetn ), //low active
.arid (cpu_arid ),
.araddr (cpu_araddr ),
.arlen (cpu_arlen ),
.arsize (cpu_arsize ),
.arburst (cpu_arburst ),
.arlock (cpu_arlock ),
.arcache (cpu_arcache ),
.arprot (cpu_arprot ),
.arvalid (cpu_arvalid ),
.arready (cpu_arready ),
.rid (cpu_rid ),
.rdata (cpu_rdata ),
.rresp (cpu_rresp ),
.rlast (cpu_rlast ),
.rvalid (cpu_rvalid ),
.rready (cpu_rready ),
.awid (cpu_awid ),
.awaddr (cpu_awaddr ),
.awlen (cpu_awlen ),
.awsize (cpu_awsize ),
.awburst (cpu_awburst ),
.awlock (cpu_awlock ),
.awcache (cpu_awcache ),
.awprot (cpu_awprot ),
.awvalid (cpu_awvalid ),
.awready (cpu_awready ),
.wid (cpu_wid ),
.wdata (cpu_wdata ),
.wstrb (cpu_wstrb ),
.wlast (cpu_wlast ),
.wvalid (cpu_wvalid ),
.wready (cpu_wready ),
.bid (cpu_bid ),
.bresp (cpu_bresp ),
.bvalid (cpu_bvalid ),
.bready (cpu_bready ),
//debug interface
.break_point (1'b0 ),
.infor_flag (1'b0 ),
.reg_num (5'b0 ),
.ws_valid ( ),
.rf_rdata ( ),
.debug0_wb_pc (debug_wb_pc ),
.debug0_wb_inst (debug_wb_inst ),
.debug0_wb_rf_wen (debug_wb_rf_wen ),
.debug0_wb_rf_wnum (debug_wb_rf_wnum ),
.debug0_wb_rf_wdata (debug_wb_rf_wdata )
);
//clock sync: from CPU to AXI_Crossbar
Axi_CDC u_Axi_CDC (
.axiInClk ( cpu_clk ),
.axiInRstn ( cpu_resetn ),
.axiOutClk ( sys_clk ),
.axiOutRstn ( sys_resetn ),
.axiIn_awvalid ( cpu_awvalid ),
.axiIn_awaddr ( cpu_awaddr ),
.axiIn_awid ( {1'b0,cpu_awid} ),
.axiIn_awlen ( cpu_awlen ),
.axiIn_awsize ( cpu_awsize ),
.axiIn_awburst ( cpu_awburst ),
.axiIn_awlock ( cpu_awlock[0] ),
.axiIn_awcache ( cpu_awcache ),
.axiIn_awprot ( cpu_awprot ),
.axiIn_wvalid ( cpu_wvalid ),
.axiIn_wdata ( cpu_wdata ),
.axiIn_wstrb ( cpu_wstrb ),
.axiIn_wlast ( cpu_wlast ),
.axiIn_bready ( cpu_bready ),
.axiIn_arvalid ( cpu_arvalid ),
.axiIn_araddr ( cpu_araddr ),
.axiIn_arid ( {1'b0,cpu_arid} ),
.axiIn_arlen ( cpu_arlen ),
.axiIn_arsize ( cpu_arsize ),
.axiIn_arburst ( cpu_arburst ),
.axiIn_arlock ( cpu_arlock[0] ),
.axiIn_arcache ( cpu_arcache ),
.axiIn_arprot ( cpu_arprot ),
.axiIn_rready ( cpu_rready ),
.axiOut_awready ( cpu_sync_awready ),
.axiOut_wready ( cpu_sync_wready ),
.axiOut_bvalid ( cpu_sync_bvalid ),
.axiOut_bid ( {1'b0,cpu_sync_bid}),
.axiOut_bresp ( cpu_sync_bresp ),
.axiOut_arready ( cpu_sync_arready ),
.axiOut_rvalid ( cpu_sync_rvalid ),
.axiOut_rdata ( cpu_sync_rdata ),
.axiOut_rid ( {1'b0,cpu_sync_rid}),
.axiOut_rresp ( cpu_sync_rresp ),
.axiOut_rlast ( cpu_sync_rlast ),
.axiIn_awready ( cpu_awready ),
.axiIn_wready ( cpu_wready ),
.axiIn_bvalid ( cpu_bvalid ),
.axiIn_bid ( {cpu_bid_4,cpu_bid} ),
.axiIn_bresp ( cpu_bresp ),
.axiIn_arready ( cpu_arready ),
.axiIn_rvalid ( cpu_rvalid ),
.axiIn_rdata ( cpu_rdata ),
.axiIn_rid ( {cpu_rid_4,cpu_rid} ),
.axiIn_rresp ( cpu_rresp ),
.axiIn_rlast ( cpu_rlast ),
.axiOut_awvalid ( cpu_sync_awvalid ),
.axiOut_awaddr ( cpu_sync_awaddr ),
.axiOut_awid ( {cpu_sync_awid_4,cpu_sync_awid}),
.axiOut_awlen ( cpu_sync_awlen ),
.axiOut_awsize ( cpu_sync_awsize ),
.axiOut_awburst ( cpu_sync_awburst ),
.axiOut_awlock ( cpu_sync_awlock ),
.axiOut_awcache ( cpu_sync_awcache ),
.axiOut_awprot ( cpu_sync_awprot ),
.axiOut_wvalid ( cpu_sync_wvalid ),
.axiOut_wdata ( cpu_sync_wdata ),
.axiOut_wstrb ( cpu_sync_wstrb ),
.axiOut_wlast ( cpu_sync_wlast ),
.axiOut_bready ( cpu_sync_bready ),
.axiOut_arvalid ( cpu_sync_arvalid ),
.axiOut_araddr ( cpu_sync_araddr ),
.axiOut_arid ( {cpu_sync_arid_4,cpu_sync_arid}),
.axiOut_arlen ( cpu_sync_arlen ),
.axiOut_arsize ( cpu_sync_arsize ),
.axiOut_arburst ( cpu_sync_arburst ),
.axiOut_arlock ( cpu_sync_arlock ),
.axiOut_arcache ( cpu_sync_arcache ),
.axiOut_arprot ( cpu_sync_arprot ),
.axiOut_rready ( cpu_sync_rready )
);
//axi ram
axi_wrap_ram_sp_external u_axi_ram (
.aclk ( sys_clk ),
.aresetn ( sys_resetn ),
//ar
.axi_arid ( ram_arid ),
.axi_araddr ( ram_araddr ),
.axi_arlen ( ram_arlen ),
.axi_arsize ( ram_arsize ),
.axi_arburst ( ram_arburst ),
.axi_arlock ( ram_arlock ),
.axi_arcache ( ram_arcache ),
.axi_arprot ( ram_arprot ),
.axi_arvalid ( ram_arvalid ),
.axi_arready ( ram_arready ),
//r
.axi_rid ( ram_rid ),
.axi_rdata ( ram_rdata ),
.axi_rresp ( ram_rresp ),
.axi_rlast ( ram_rlast ),
.axi_rvalid ( ram_rvalid ),
.axi_rready ( ram_rready ),
//aw
.axi_awid ( ram_awid ),
.axi_awaddr ( ram_awaddr ),
.axi_awlen ( ram_awlen ),
.axi_awsize ( ram_awsize ),
.axi_awburst ( ram_awburst ),
.axi_awlock ( ram_awlock ),
.axi_awcache ( ram_awcache ),
.axi_awprot ( ram_awprot ),
.axi_awvalid ( ram_awvalid ),
.axi_awready ( ram_awready ),
//w
.axi_wdata ( ram_wdata ),
.axi_wstrb ( ram_wstrb ),
.axi_wlast ( ram_wlast ),
.axi_wvalid ( ram_wvalid ),
.axi_wready ( ram_wready ),
//b ram
.axi_bid ( ram_bid ),
.axi_bresp ( ram_bresp ),
.axi_bvalid ( ram_bvalid ),
.axi_bready ( ram_bready ),
.base_ram_addr ( base_ram_addr ),
.base_ram_be_n ( base_ram_be_n ),
.base_ram_ce_n ( base_ram_ce_n ),
.base_ram_oe_n ( base_ram_oe_n ),
.base_ram_we_n ( base_ram_we_n ),
.ext_ram_addr ( ext_ram_addr ),
.ext_ram_be_n ( ext_ram_be_n ),
.ext_ram_ce_n ( ext_ram_ce_n ),
.ext_ram_oe_n ( ext_ram_oe_n ),
.ext_ram_we_n ( ext_ram_we_n ),
.base_ram_data ( base_ram_data ),
.ext_ram_data ( ext_ram_data )
);
//AXI2APB
axi_uart_controller u_axi_uart_controller
(
.clk (sys_clk ),
.rst_n (sys_resetn ),
.axi_s_awid (uart_awid ),
.axi_s_awaddr (uart_awaddr ),
.axi_s_awlen (uart_awlen ),
.axi_s_awsize (uart_awsize ),
.axi_s_awburst (uart_awburst ),
.axi_s_awlock (uart_awlock ),
.axi_s_awcache (uart_awcache ),
.axi_s_awprot (uart_awprot ),
.axi_s_awvalid (uart_awvalid ),
.axi_s_awready (uart_awready ),
.axi_s_wid (uart_awid ),
.axi_s_wdata (uart_wdata ),
.axi_s_wstrb (uart_wstrb ),
.axi_s_wlast (uart_wlast ),
.axi_s_wvalid (uart_wvalid ),
.axi_s_wready (uart_wready ),
.axi_s_bid (uart_bid ),
.axi_s_bresp (uart_bresp ),
.axi_s_bvalid (uart_bvalid ),
.axi_s_bready (uart_bready ),
.axi_s_arid (uart_arid ),
.axi_s_araddr (uart_araddr ),
.axi_s_arlen (uart_arlen ),
.axi_s_arsize (uart_arsize ),
.axi_s_arburst (uart_arburst ),
.axi_s_arlock (uart_arlock ),
.axi_s_arcache (uart_arcache ),
.axi_s_arprot (uart_arprot ),
.axi_s_arvalid (uart_arvalid ),
.axi_s_arready (uart_arready ),
.axi_s_rid (uart_rid ),
.axi_s_rdata (uart_rdata ),
.axi_s_rresp (uart_rresp ),
.axi_s_rlast (uart_rlast ),
.axi_s_rvalid (uart_rvalid ),
.axi_s_rready (uart_rready ),
.apb_rw_dma (1'b0 ),
.apb_psel_dma (1'b0 ),
.apb_enab_dma (1'b0 ),
.apb_addr_dma (20'b0 ),
.apb_valid_dma (1'b0 ),
.apb_wdata_dma (32'b0 ),
.apb_rdata_dma ( ),
.apb_ready_dma ( ),
.dma_grant ( ),
.dma_req_o ( ),
.dma_ack_i (1'b0 ),
//UART0
.uart0_txd_i (uart0_txd_i ),
.uart0_txd_o (uart0_txd_o ),
.uart0_txd_oe (uart0_txd_oe ),
.uart0_rxd_i (uart0_rxd_i ),
.uart0_rxd_o (uart0_rxd_o ),
.uart0_rxd_oe (uart0_rxd_oe ),
.uart0_rts_o (uart0_rts_o ),
.uart0_dtr_o (uart0_dtr_o ),
.uart0_cts_i (uart0_cts_i ),
.uart0_dsr_i (uart0_dsr_i ),
.uart0_dcd_i (uart0_dcd_i ),
.uart0_ri_i (uart0_ri_i ),
.uart0_int (uart0_int )
);
confreg #(
.SIMULATION(SIMULATION)
) u_confreg (
// 时钟与复位
.aclk (sys_clk), // AXI总线时钟
.aresetn (sys_resetn), // AXI总线复位
.cpu_clk (cpu_clk), // CPU时钟
.cpu_resetn (cpu_resetn), // CPU复位
// AXI写地址通道
.s_awid (confreg_awid),
.s_awaddr (confreg_awaddr),
.s_awlen (confreg_awlen),
.s_awsize (confreg_awsize),
.s_awburst (confreg_awburst),
.s_awlock (confreg_awlock),
.s_awcache (confreg_awcache),
.s_awprot (confreg_awprot),
.s_awvalid (confreg_awvalid),
.s_awready (confreg_awready),
// AXI写数据通道
.s_wid (confreg_wid),
.s_wdata (confreg_wdata),
.s_wstrb (confreg_wstrb),
.s_wlast (confreg_wlast),
.s_wvalid (confreg_wvalid),
.s_wready (confreg_wready),
// AXI写响应通道
.s_bid (confreg_bid),
.s_bresp (confreg_bresp),
.s_bvalid (confreg_bvalid),
.s_bready (confreg_bready),
// AXI读地址通道
.s_arid (confreg_arid),
.s_araddr (confreg_araddr),
.s_arlen (confreg_arlen),
.s_arsize (confreg_arsize),
.s_arburst (confreg_arburst),
.s_arlock (confreg_arlock),
.s_arcache (confreg_arcache),
.s_arprot (confreg_arprot),
.s_arvalid (confreg_arvalid),
.s_arready (confreg_arready),
// AXI读数据通道
.s_rid (confreg_rid),
.s_rdata (confreg_rdata),
.s_rresp (confreg_rresp),
.s_rlast (confreg_rlast),
.s_rvalid (confreg_rvalid),
.s_rready (confreg_rready),
// IO外设接口 (与soc_top顶层引脚相连)
.led (leds), // 顶层引脚名称为
.dpy0 (dpy0), // 低位数码管
.dpy1 (dpy1), // 高位数码管
.switch (dip_sw), // 拨码开关，顶层名称为 dip_sw
.touch_btn (touch_btn), // 触摸按钮
// 中断与状态信号
.dma_finish (dma_finish), // DMA完成信号
.fft_finish (fft_finish), // FFT完成信号
.confreg_int(confreg_int) // 输出中断给CPU
);
axi_dvi u_axi_dvi (
.s_awvalid ( dvi_awvalid ),
.s_awaddr ( dvi_awaddr ),
.s_awid ( dvi_awid ),
.s_awlen ( dvi_awlen ),
.s_awsize ( dvi_awsize ),
.s_awburst ( dvi_awburst ),
.s_awlock ( dvi_awlock ),
.s_awcache ( dvi_awcache ),
.s_awprot ( dvi_awprot ),
.s_wvalid ( dvi_wvalid ),
.s_wdata ( dvi_wdata ),
.s_wstrb ( dvi_wstrb ),
.s_wlast ( dvi_wlast ),
.s_bready ( dvi_bready ),
.s_arvalid ( dvi_arvalid ),
.s_araddr ( dvi_araddr ),
.s_arid ( dvi_arid ),
.s_arlen ( dvi_arlen ),
.s_arsize ( dvi_arsize ),
.s_arburst ( dvi_arburst ),
.s_arlock ( dvi_arlock ),
.s_arcache ( dvi_arcache ),
.s_arprot ( dvi_arprot ),
.s_rready ( dvi_rready ),
.aclk ( sys_clk ),
.aresetn ( sys_resetn ),
.s_awready ( dvi_awready ),
.s_wready ( dvi_wready ),
.s_bvalid ( dvi_bvalid ),
.s_bid ( dvi_bid ),
.s_bresp ( dvi_bresp ),
.s_arready ( dvi_arready ),
.s_rvalid ( dvi_rvalid ),
.s_rdata ( dvi_rdata ),
.s_rid ( dvi_rid ),
.s_rresp ( dvi_rresp ),
.s_rlast ( dvi_rlast ),
.video_clk ( video_clk ),
.hsync ( video_hsync ),
.vsync ( video_vsync ),
.data_enable ( video_de ),
.video_red ( video_red ),
.video_green ( video_green ),
.video_blue ( video_blue )
);
fft_controller u_fft_controller(
.aclk (sys_clk ),
.aresetn (sys_resetn ),
.s_awid (fft_awid ),
.s_awaddr (fft_awaddr ),
.s_awlen (fft_awlen ),
.s_awsize (fft_awsize ),
.s_awburst (fft_awburst ),
.s_awlock (fft_awlock ),
.s_awcache (fft_awcache ),
.s_awprot (fft_awprot ),
.s_awvalid (fft_awvalid ),
.s_awready (fft_awready ),
.s_wid (fft_wid ),
.s_wdata (fft_wdata ),
.s_wstrb (fft_wstrb ),
.s_wlast (fft_wlast ),
.s_wvalid (fft_wvalid ),
.s_wready (fft_wready ),
.s_bid (fft_bid ),
.s_bresp (fft_bresp ),
.s_bvalid (fft_bvalid ),
.s_bready (fft_bready ),
.s_arid (fft_arid ),
.s_araddr (fft_araddr ),
.s_arlen (fft_arlen ),
.s_arsize (fft_arsize ),
.s_arburst (fft_arburst ),
.s_arlock (fft_arlock ),
.s_arcache (fft_arcache ),
.s_arprot (fft_arprot ),
.s_arvalid (fft_arvalid ),
.s_arready (fft_arready ),
.s_rid (fft_rid ),
.s_rdata (fft_rdata ),
.s_rresp (fft_rresp ),
.s_rlast (fft_rlast ),
.s_rvalid (fft_rvalid ),
.s_rready (fft_rready ),
.fft_finish (fft_finish )
);
// assign dma_m_arid = 4'b0 ;
// assign dma_m_araddr = 32'h0;
// assign dma_m_arlen = 8'b0 ;
// assign dma_m_arsize = 3'b0 ;
// assign dma_m_arburst = 2'b0;
// assign dma_m_arlock = 1'b0;
// assign dma_m_arcache = 4'b0;
// assign dma_m_arprot = 3'b0;
// assign dma_m_arvalid = 1'b0;
// assign dma_m_rready = 1'b1;
// assign dma_m_awid = 4'b0;
// assign dma_m_awaddr = 32'b0;
// assign dma_m_awlen = 8'b0;
// assign dma_m_awsize = 3'b0;
// assign dma_m_awburst = 2'b0;
// assign dma_m_awlock = 1'b0;
// assign dma_m_awcache = 4'b0;
// assign dma_m_awprot = 3'b0;
// assign dma_m_awvalid = 1'b0;
// assign dma_m_wid = 4'b0;
// assign dma_m_wdata = 32'b0;
// assign dma_m_wstrb = 4'b0;
// assign dma_m_wlast = 1'b0;
// assign dma_m_wvalid = 1'b0;
// assign dma_m_bready = 1'b1;
// assign dma_s_arready = 1'b1;
// assign dma_s_rid = 5'b0;
// assign dma_s_rdata = 32'b0;
// assign dma_s_rresp = 2'b0;
// assign dma_s_rlast = 1'b0;
// assign dma_s_rvalid = 1'b0;
// assign dma_s_awready = 1'b1;
// assign dma_s_wready = 1'b1;
// assign dma_s_bid = 5'b0;
// assign dma_s_bresp = 2'b0;
// assign dma_s_bvalid = 1'b0;
wire [31:0] cdma_s_awaddr;
wire [2:0] cdma_s_awprot;
wire cdma_s_awvalid;
wire cdma_s_awready;
wire [31:0] cdma_s_wdata;
wire [3:0] cdma_s_wstrb;
wire cdma_s_wvalid;
wire cdma_s_wready;
wire [1:0] cdma_s_bresp;
wire cdma_s_bvalid;
wire cdma_s_bready;
wire [31:0] cdma_s_araddr;
wire [2:0] cdma_s_arprot;
wire cdma_s_arvalid;
wire cdma_s_arready;
wire [31:0] cdma_s_rdata;
wire [1:0] cdma_s_rresp;
wire cdma_s_rvalid;
wire cdma_s_rready;
axi_axil_adapter #(
.ADDR_WIDTH(32),
.AXI_DATA_WIDTH(32),
.AXI_ID_WIDTH(5),
.AXIL_DATA_WIDTH(32),
.CONVERT_BURST(1),
.CONVERT_NARROW_BURST(0)
)
u_axi_axil_adapter(
.clk(sys_clk),
.rst(~sys_resetn),
.s_axi_awid(dma_s_awid),
.s_axi_awaddr(dma_s_awaddr),
.s_axi_awlen(dma_s_awlen),
.s_axi_awsize(dma_s_awsize),
.s_axi_awburst(dma_s_awburst),
.s_axi_awlock(dma_s_awlock),
.s_axi_awcache(dma_s_awcache),
.s_axi_awprot(dma_s_awprot),
.s_axi_awvalid(dma_s_awvalid),
.s_axi_awready(dma_s_awready),
.s_axi_wdata(dma_s_wdata),
.s_axi_wstrb(dma_s_wstrb),
.s_axi_wlast(dma_s_wlast),
.s_axi_wvalid(dma_s_wvalid),
.s_axi_wready(dma_s_wready),
.s_axi_bid(dma_s_bid),
.s_axi_bresp(dma_s_bresp),
.s_axi_bvalid(dma_s_bvalid),
.s_axi_bready(dma_s_bready),
.s_axi_arid(dma_s_arid),
.s_axi_araddr(dma_s_araddr),
.s_axi_arlen(dma_s_arlen),
.s_axi_arsize(dma_s_arsize),
.s_axi_arburst(dma_s_arburst),
.s_axi_arlock(dma_s_arlock),
.s_axi_arcache(dma_s_arcache),
.s_axi_arprot(dma_s_arprot),
.s_axi_arvalid(dma_s_arvalid),
.s_axi_arready(dma_s_arready),
.s_axi_rid(dma_s_rid),
.s_axi_rdata(dma_s_rdata),
.s_axi_rresp(dma_s_rresp),
.s_axi_rlast(dma_s_rlast),
.s_axi_rvalid(dma_s_rvalid),
.s_axi_rready(dma_s_rready),
.m_axil_awaddr(cdma_s_awaddr),
.m_axil_awprot(cdma_s_awprot),
.m_axil_awvalid(cdma_s_awvalid),
.m_axil_awready(cdma_s_awready),
.m_axil_wdata(cdma_s_wdata),
.m_axil_wstrb(cdma_s_wstrb),
.m_axil_wvalid(cdma_s_wvalid),
.m_axil_wready(cdma_s_wready),
.m_axil_bresp(cdma_s_bresp),
.m_axil_bvalid(cdma_s_bvalid),
.m_axil_bready(cdma_s_bready),
.m_axil_araddr(cdma_s_araddr),
.m_axil_arprot(cdma_s_arprot),
.m_axil_arvalid(cdma_s_arvalid),
.m_axil_arready(cdma_s_arready),
.m_axil_rdata(cdma_s_rdata),
.m_axil_rresp(cdma_s_rresp),
.m_axil_rvalid(cdma_s_rvalid),
.m_axil_rready(cdma_s_rready)
);
snix_axi_cdma #(
.ADDR_WIDTH (32 ),
.DATA_WIDTH (32 ),
.AXIL_ADDR_WIDTH (32 ),
.AXIL_DATA_WIDTH (32 ),
.ID_WIDTH (4 ),
.USER_WIDTH (1 ))
u_snix_axi_cdma(
.clk (sys_clk ),
.rst_n (sys_resetn ),
.s_axil_awaddr (cdma_s_awaddr ),
.s_axil_awvalid (cdma_s_awvalid ),
.s_axil_awready (cdma_s_awready ),
.s_axil_wdata (cdma_s_wdata ),
.s_axil_wstrb (cdma_s_wstrb ),
.s_axil_wvalid (cdma_s_wvalid ),
.s_axil_wready (cdma_s_wready ),
.s_axil_bresp (cdma_s_bresp ),
.s_axil_bvalid (cdma_s_bvalid ),
.s_axil_bready (cdma_s_bready ),
.s_axil_araddr (cdma_s_araddr ),
.s_axil_arvalid (cdma_s_arvalid ),
.s_axil_arready (cdma_s_arready ),
.s_axil_rdata (cdma_s_rdata ),
.s_axil_rresp (cdma_s_rresp ),
.s_axil_rvalid (cdma_s_rvalid ),
.s_axil_rready (cdma_s_rready ),
.mm2mm_awid (dma_m_awid ),
.mm2mm_awaddr (dma_m_awaddr ),
.mm2mm_awlen (dma_m_awlen ),
.mm2mm_awsize (dma_m_awsize ),
.mm2mm_awburst (dma_m_awburst ),
.mm2mm_awlock (dma_m_awlock ),
.mm2mm_awcache (dma_m_awcache ),
.mm2mm_awprot (dma_m_awprot ),
.mm2mm_awqos ( ),
.mm2mm_awuser ( ),
.mm2mm_awvalid (dma_m_awvalid ),
.mm2mm_awready (dma_m_awready ),
.mm2mm_wdata (dma_m_wdata ),
.mm2mm_wstrb (dma_m_wstrb ),
.mm2mm_wlast (dma_m_wlast ),
.mm2mm_wuser ( ),
.mm2mm_wvalid (dma_m_wvalid ),
.mm2mm_wready (dma_m_wready ),
.mm2mm_bid (dma_m_bid ),
.mm2mm_bresp (dma_m_bresp ),
.mm2mm_buser (1'b0),
.mm2mm_bvalid (dma_m_bvalid ),
.mm2mm_bready (dma_m_bready ),
.mm2mm_arid (dma_m_arid ),
.mm2mm_araddr (dma_m_araddr ),
.mm2mm_arlen (dma_m_arlen ),
.mm2mm_arsize (dma_m_arsize ),
.mm2mm_arburst (dma_m_arburst ),
.mm2mm_arlock (dma_m_arlock ),
.mm2mm_arcache (dma_m_arcache ),
.mm2mm_arprot (dma_m_arprot ),
.mm2mm_arqos ( ),
.mm2mm_aruser ( ),
.mm2mm_arvalid (dma_m_arvalid ),
.mm2mm_arready (dma_m_arready ),
.mm2mm_rid (dma_m_rid ),
.mm2mm_rdata (dma_m_rdata ),
.mm2mm_rresp (dma_m_rresp ),
.mm2mm_rlast (dma_m_rlast ),
.mm2mm_ruser (1'b0),
.mm2mm_rvalid (dma_m_rvalid ),
.mm2mm_rready (dma_m_rready ),
.dma_finish (dma_finish)
);
endmodule