680 lines
31 KiB
Plaintext
680 lines
31 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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<<<<<<< Updated upstream
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| Date : Fri Jul 10 04:14:46 2026
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=======
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| Date : Sat Jul 11 09:20:51 2026
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>>>>>>> Stashed changes
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| Host : fedora running 64-bit unknown
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| Command : report_methodology -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/methodology.rpt
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| Design : soc_top
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| Device : xc7a200tfbg676-1
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| Speed File : -1
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| Design State : Fully Routed
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Report Methodology
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: impl_1
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Design limits: <entire design considered>
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Max violations: <unlimited>
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<<<<<<< Updated upstream
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Violations found: 107
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=======
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Violations found: 115
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>>>>>>> Stashed changes
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+-----------+----------+-------------------------------------------------------------------+------------+
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| Rule | Severity | Description | Violations |
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+-----------+----------+-------------------------------------------------------------------+------------+
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| LUTAR-1 | Warning | LUT drives async reset alert | 1 |
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| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 |
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<<<<<<< Updated upstream
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| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 9 |
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| SYNTH-16 | Warning | Address collision | 8 |
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=======
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| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 6 |
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| SYNTH-16 | Warning | Address collision | 16 |
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| TIMING-9 | Warning | Unknown CDC Logic | 1 |
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>>>>>>> Stashed changes
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| TIMING-10 | Warning | Missing property on synchronizer | 1 |
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| TIMING-18 | Warning | Missing input or output delay | 76 |
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| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 4 |
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| XDCC-1 | Warning | Scoped Clock constraint overwritten with the same name | 1 |
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| XDCC-7 | Warning | Scoped Clock constraint overwritten on the same source | 1 |
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+-----------+----------+-------------------------------------------------------------------+------------+
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2. REPORT DETAILS
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-----------------
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LUTAR-1#1 Warning
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LUT drives async reset alert
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<<<<<<< Updated upstream
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LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24656 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
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=======
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LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/FSM_sequential_state_r[2]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 15633 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-5#1 Warning
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Mapped onto distributed RAM because of timing constraints
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The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
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Related violations: <none>
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SYNTH-5#2 Warning
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Mapped onto distributed RAM because of timing constraints
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The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
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Related violations: <none>
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SYNTH-5#3 Warning
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Mapped onto distributed RAM because of timing constraints
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The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
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Related violations: <none>
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SYNTH-5#4 Warning
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Mapped onto distributed RAM because of timing constraints
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The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
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Related violations: <none>
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SYNTH-5#5 Warning
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Mapped onto distributed RAM because of timing constraints
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The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
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Related violations: <none>
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SYNTH-5#6 Warning
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Mapped onto distributed RAM because of timing constraints
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The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
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Related violations: <none>
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SYNTH-5#7 Warning
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Mapped onto distributed RAM because of timing constraints
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The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
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Related violations: <none>
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SYNTH-5#8 Warning
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Mapped onto distributed RAM because of timing constraints
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The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
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Related violations: <none>
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SYNTH-6#1 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-6#2 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-6#3 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-6#4 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-6#5 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-6#6 Warning
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Timing of a block RAM might be sub-optimal
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<<<<<<< Updated upstream
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The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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Related violations: <none>
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SYNTH-6#7 Warning
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Timing of a block RAM might be sub-optimal
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The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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Related violations: <none>
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SYNTH-6#8 Warning
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Timing of a block RAM might be sub-optimal
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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Related violations: <none>
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SYNTH-6#9 Warning
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Timing of a block RAM might be sub-optimal
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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=======
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The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
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>>>>>>> Stashed changes
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Related violations: <none>
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SYNTH-16#1 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#2 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#3 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#4 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#5 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#6 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#7 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#8 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#9 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[0].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#10 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[1].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#11 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[2].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#12 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_cr/gen_xbar[3].u_bank/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#13 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#14 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_a_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#15 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_even/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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SYNTH-16#16 Warning
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Address collision
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Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_b_odd/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
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Related violations: <none>
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TIMING-9#1 Warning
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Unknown CDC Logic
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One or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities
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Related violations: <none>
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TIMING-10#1 Warning
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Missing property on synchronizer
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One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage
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Related violations: <none>
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TIMING-18#1 Warning
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Missing input or output delay
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An input delay is missing on UART_RX relative to clock(s) clk
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Related violations: <none>
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TIMING-18#2 Warning
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Missing input or output delay
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An input delay is missing on UART_TX relative to clock(s) clk
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Related violations: <none>
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TIMING-18#3 Warning
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Missing input or output delay
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An input delay is missing on dip_sw[0] relative to clock(s) clk
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Related violations: <none>
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TIMING-18#4 Warning
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Missing input or output delay
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An input delay is missing on dip_sw[10] relative to clock(s) clk
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Related violations: <none>
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TIMING-18#5 Warning
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Missing input or output delay
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An input delay is missing on dip_sw[11] relative to clock(s) clk
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Related violations: <none>
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TIMING-18#6 Warning
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Missing input or output delay
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An input delay is missing on dip_sw[12] relative to clock(s) clk
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Related violations: <none>
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TIMING-18#7 Warning
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Missing input or output delay
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An input delay is missing on dip_sw[13] relative to clock(s) clk
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Related violations: <none>
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TIMING-18#8 Warning
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Missing input or output delay
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An input delay is missing on dip_sw[14] relative to clock(s) clk
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Related violations: <none>
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TIMING-18#9 Warning
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Missing input or output delay
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An input delay is missing on dip_sw[15] relative to clock(s) clk
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Related violations: <none>
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TIMING-18#10 Warning
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Missing input or output delay
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An input delay is missing on dip_sw[16] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#11 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[17] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#12 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[18] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#13 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[19] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#14 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#15 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[20] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#16 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[21] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#17 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[22] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#18 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[23] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#19 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[24] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#20 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[25] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#21 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[26] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#22 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[27] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#23 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[28] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#24 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[29] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#25 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#26 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[30] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#27 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[31] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#28 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[3] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#29 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[4] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#30 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[5] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#31 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[6] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#32 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[7] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#33 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[8] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#34 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[9] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#35 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on touch_btn[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#36 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on touch_btn[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#37 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on touch_btn[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#38 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on touch_btn[3] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#39 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#40 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#41 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#42 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[3] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#43 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[4] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#44 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[5] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#45 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[6] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#46 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[7] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#47 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#48 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#49 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#50 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[3] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#51 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[4] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#52 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[5] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#53 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[6] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#54 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[7] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#55 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#56 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[10] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#57 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[11] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#58 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[12] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#59 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[13] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#60 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[14] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#61 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[15] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#62 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#63 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#64 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[3] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#65 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[4] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#66 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[5] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#67 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[6] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#68 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[7] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#69 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[8] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#70 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[9] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#71 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_de relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#72 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_hsync relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#73 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_red[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#74 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_red[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#75 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_red[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#76 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_vsync relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-47#1 Warning
|
|
False path or asynchronous clock group between synchronous clocks
|
|
A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
|
|
Related violations: <none>
|
|
|
|
TIMING-47#2 Warning
|
|
False path or asynchronous clock group between synchronous clocks
|
|
A Clock Group timing constraint is set between synchronous clocks mlkem_clk and sys_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
|
|
Related violations: <none>
|
|
|
|
TIMING-47#3 Warning
|
|
False path or asynchronous clock group between synchronous clocks
|
|
A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
|
|
Related violations: <none>
|
|
|
|
TIMING-47#4 Warning
|
|
False path or asynchronous clock group between synchronous clocks
|
|
A Clock Group timing constraint is set between synchronous clocks sys_clk and mlkem_clk (see constraint position 7 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
|
|
Related violations: <none>
|
|
|
|
XDCC-1#1 Warning
|
|
Scoped Clock constraint overwritten with the same name
|
|
A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
|
|
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
|
|
Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
|
|
Related violations: <none>
|
|
|
|
XDCC-7#1 Warning
|
|
Scoped Clock constraint overwritten on the same source
|
|
A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
|
|
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
|
|
Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
|
|
Related violations: <none>
|
|
|
|
|