35 lines
992 B
Verilog
35 lines
992 B
Verilog
//----------------------------------------------------------------------
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// DelayBuffer: Generate Constant Delay
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//----------------------------------------------------------------------
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module DelayBuffer #(
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parameter DEPTH = 32,
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parameter WIDTH = 16
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)(
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input clock, // Master Clock
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input [WIDTH-1:0] di_re, // Data Input (Real)
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input [WIDTH-1:0] di_im, // Data Input (Imag)
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output [WIDTH-1:0] do_re, // Data Output (Real)
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output [WIDTH-1:0] do_im // Data Output (Imag)
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);
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reg [WIDTH-1:0] buf_re[0:DEPTH-1];
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reg [WIDTH-1:0] buf_im[0:DEPTH-1];
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integer n;
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// Shift Buffer
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/* verilator lint_off BLKLOOPINIT */
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always @(posedge clock) begin
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for (n = DEPTH-1; n > 0; n = n - 1) begin
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buf_re[n] <= buf_re[n-1];
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buf_im[n] <= buf_im[n-1];
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end
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buf_re[0] <= di_re;
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buf_im[0] <= di_im;
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end
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/* verilator lint_on BLKLOOPINIT */
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assign do_re = buf_re[DEPTH-1];
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assign do_im = buf_im[DEPTH-1];
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endmodule
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