FallenSigh
e35fa5884d
The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000 go to the write-back data cache and never reach the SRAM model before the testbench checks ExtRAM. Use the 0xA0000000 uncached segment (same pattern as fft_dma/main.c).
20 lines
790 B
Plaintext
20 lines
790 B
Plaintext
fft_csr init = 0
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--- Starting Hardware FFT with DMA ---
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--- Starting Software FFT ---
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--- Performance Comparison ---
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Timer Clock Freq : 50000000 Hz
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Hardware FFT Time: 407310 ns (0.407 ms)
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Software FFT Time: 274786920 ns (274.787 ms)
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Speedup Ratio : 674.64x
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--- Verification (Only showing Bins with energy > 10) ---
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Bin [ 0] Hz: HW(Re: 4007, Im: 0) | SW(Re: 4000, Im: 0)
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Bin [ 10] Hz: HW(Re: 4006, Im: -1) | SW(Re: 3999, Im: 0)
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Bin [ 200] Hz: HW(Re: 2, Im: -2994) | SW(Re: 0, Im: -3000)
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Bin [ 400] Hz: HW(Re: -5, Im: -1496) | SW(Re: 0, Im: -1499)
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Bin [ 624] Hz: HW(Re: -5, Im: 1497) | SW(Re: 0, Im: 1500)
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Bin [ 824] Hz: HW(Re: 3, Im: 2994) | SW(Re: 0, Im: 2999)
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Bin [1014] Hz: HW(Re: 4007, Im: 0) | SW(Re: 3999, Im: 0)
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