53 lines
3.3 KiB
Plaintext
53 lines
3.3 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 03:34:29 2026
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| Host : fedora running 64-bit unknown
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| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt
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| Design : soc_top
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| Device : xc7a200t
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| Design State : Routed
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Report Design Analysis
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Table of Contents
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-----------------
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1. Setup Path Characteristics 1-1
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1. Setup Path Characteristics 1-1
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---------------------------------
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+---------------------------+------------------------------------------------------+
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| Characteristics | Path #1 |
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+---------------------------+------------------------------------------------------+
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| Requirement | 20.000 |
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| Path Delay | 15.605 |
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| Logic Delay | 5.343(35%) |
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| Net Delay | 10.263(65%) |
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| Clock Skew | -3.858 |
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| Slack | 0.167 |
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| Clock Relationship | Safely Timed |
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| Logic Levels | 9 |
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| Routes | 9 |
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| Logical Path | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT |
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| Start Point Clock | sys_clk |
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| End Point Clock | sys_clk |
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| DSP Block | None |
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| BRAM | None |
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| IO Crossings | 3 |
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| Config Crossings | 0 |
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| SLR Crossings | 0 |
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| PBlocks | 0 |
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| High Fanout | 130 |
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| Dont Touch | 0 |
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| Mark Debug | 0 |
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| Start Point Pin Primitive | FDRE/C |
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| End Point Pin Primitive | ext_ram_data[18] |
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| Start Point Pin | FSM_sequential_ext_wr_state_reg[1]/C |
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| End Point Pin | ext_ram_data[18] |
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+---------------------------+------------------------------------------------------+
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* Bounding box calculated as % of dimensions for the target device (436, 500)
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