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FallenSigh db9997b473 Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state

2026-06-25 22:09:20 +08:00

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ip

Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state

2026-06-25 22:09:20 +08:00

config.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

soc_top.v

Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines

2026-06-25 20:03:53 +08:00