FallenSigh
4538ec496f
At mlkem_clk=100 MHz the worst path (WNS -2.14 ns) was coeff_bram read -> butterfly diff (b-a) -> barrett first multiply stage, all in one cycle. The butterfly took its operands combinationally from the BRAM read (unlike poly_mul's basecase, which already registers them). Add an input register stage (a/b/zeta/mode/valid) in butterfly_unit_pipe so the BRAM read and the first multiply land in separate cycles; feed the a/b/mode alignment delay lines from the registered inputs. Butterfly latency 8->9; ntt_core writeback address delay lines deepened 9->10 to match. Verified byte-exact vs NIST KAT: NTT standalone TB 19/19 (fwd+inv), Encaps 9/9, Decaps 9/9, hello_world e2e — all PASS. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
90 lines
3.5 KiB
Verilog
90 lines
3.5 KiB
Verilog
// butterfly_unit_pipe.v - pipelined Cooley-Tukey / Gentleman-Sande butterfly
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//
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// Fixed-latency wrapper around barrett_mul_pipe. All arithmetic that used to
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// sit in one NTT cycle is now split by registers.
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module butterfly_unit_pipe (
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input clk,
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input rst_n,
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input valid_i,
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input [11:0] a,
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input [11:0] b,
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input [11:0] zeta,
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input mode, // 0 = forward NTT, 1 = inverse NTT
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output [11:0] a_out,
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output [11:0] b_out,
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output valid_o
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);
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localparam [11:0] Q12 = 12'd3329;
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localparam [12:0] Q13 = 13'd3329;
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// Plan A: register the inputs. Operands arrive combinationally from the
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// coeff_bram read; without this stage the path coeff_bram-read -> diff ->
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// first multiply stage sits in one cycle (the mlkem_clk critical path at
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// 100 MHz). Registering here splits it into (BRAM read -> reg) and
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// (reg -> diff -> multiply). Adds one pipeline cycle (absorbed by the NTT
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// writeback delay line).
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reg [11:0] a_r, b_r, zeta_r;
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reg mode_ri, vld_r;
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wire [11:0] diff = (b_r >= a_r) ? (b_r - a_r) : (b_r - a_r + Q12);
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wire [11:0] mul_data = mode_ri ? diff : b_r;
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wire [11:0] mul_result;
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wire mul_valid;
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barrett_mul_pipe u_barrett (
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.clk(clk),
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.rst_n(rst_n),
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.valid_i(vld_r),
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.a(zeta_r),
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.b(mul_data),
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.product(mul_result),
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.valid_o(mul_valid)
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);
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// a/b/mode delay lines (fed from the REGISTERED inputs a_r/b_r/mode_ri so
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// a_d6 aligns with mul_valid = valid_i delayed 8).
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reg [11:0] a_d0, a_d1, a_d2, a_d3, a_d4, a_d5, a_d6;
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reg [11:0] b_d0, b_d1, b_d2, b_d3, b_d4, b_d5, b_d6;
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reg mode_d0, mode_d1, mode_d2, mode_d3, mode_d4, mode_d5, mode_d6;
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reg [11:0] a_out_r, b_out_r;
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reg valid_r;
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wire [12:0] a_sum = {1'b0, a_d6} + {1'b0, (mode_d6 ? b_d6 : mul_result)};
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wire [11:0] a_mod = (a_sum >= Q13) ? (a_sum[11:0] - Q12) : a_sum[11:0];
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wire [11:0] b_sub = (a_d6 >= mul_result) ? (a_d6 - mul_result) :
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(a_d6 - mul_result + Q12);
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assign a_out = a_out_r;
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assign b_out = b_out_r;
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assign valid_o = valid_r;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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a_r <= 12'd0; b_r <= 12'd0; zeta_r <= 12'd0; mode_ri <= 1'b0; vld_r <= 1'b0;
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a_d0 <= 12'd0; a_d1 <= 12'd0; a_d2 <= 12'd0; a_d3 <= 12'd0; a_d4 <= 12'd0; a_d5 <= 12'd0; a_d6 <= 12'd0;
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b_d0 <= 12'd0; b_d1 <= 12'd0; b_d2 <= 12'd0; b_d3 <= 12'd0; b_d4 <= 12'd0; b_d5 <= 12'd0; b_d6 <= 12'd0;
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mode_d0 <= 1'b0; mode_d1 <= 1'b0; mode_d2 <= 1'b0; mode_d3 <= 1'b0; mode_d4 <= 1'b0; mode_d5 <= 1'b0; mode_d6 <= 1'b0;
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a_out_r <= 12'd0;
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b_out_r <= 12'd0;
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valid_r <= 1'b0;
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end else begin
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// input register stage
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a_r <= a; b_r <= b; zeta_r <= zeta; mode_ri <= mode; vld_r <= valid_i;
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a_d0 <= a_r; a_d1 <= a_d0; a_d2 <= a_d1; a_d3 <= a_d2; a_d4 <= a_d3; a_d5 <= a_d4; a_d6 <= a_d5;
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b_d0 <= b_r; b_d1 <= b_d0; b_d2 <= b_d1; b_d3 <= b_d2; b_d4 <= b_d3; b_d5 <= b_d4; b_d6 <= b_d5;
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mode_d0 <= mode_ri; mode_d1 <= mode_d0; mode_d2 <= mode_d1;
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mode_d3 <= mode_d2; mode_d4 <= mode_d3; mode_d5 <= mode_d4; mode_d6 <= mode_d5;
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valid_r <= mul_valid;
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if (mul_valid) begin
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a_out_r <= a_mod;
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b_out_r <= mode_d6 ? mul_result : b_sub;
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end
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end
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end
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endmodule
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