230 lines
33 KiB
Plaintext
230 lines
33 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
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| Date : Wed Jul 15 05:09:25 2026
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| Host : Roc_Wang running 64-bit major release (build 9200)
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| Command : report_utilization -hierarchical -hierarchical_depth 4 -file C:/Users/11747/Desktop/ciciec2026/doc/reports/system/evidence/vivado/utilization_hierarchical.rpt
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| Design : soc_top
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| Device : 7a200tfbg676-1
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| Design State : Routed
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Utilization Design Information
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Table of Contents
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-----------------
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1. Utilization by Hierarchy
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1. Utilization by Hierarchy
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---------------------------
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+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
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| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
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+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
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| soc_top | (top) | 55066 | 53158 | 740 | 1168 | 31000 | 10 | 39 | 0 |
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| (soc_top) | (top) | 927 | 919 | 8 | 0 | 4 | 0 | 0 | 0 |
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| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| inst | clk_pll_clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
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| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
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| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
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| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 368 | 368 | 0 | 0 | 151 | 0 | 0 | 0 |
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| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
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| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 |
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| cmdArbiter | StreamArbiter_7_92 | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 |
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| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_75 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
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| cmdArbiter | StreamArbiter_7_91 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
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| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_76 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 |
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| cmdArbiter | StreamArbiter_7_90 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 |
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| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_77 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
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| cmdArbiter | StreamArbiter_7_89 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
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| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 32 | 32 | 0 | 0 | 11 | 0 | 0 | 0 |
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| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
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| cmdArbiter | StreamArbiter_7_86 | 26 | 26 | 0 | 0 | 3 | 0 | 0 | 0 |
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| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_87 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
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| fifo | StreamFifo_3_88 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
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| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
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| cmdArbiter | StreamArbiter_7_83 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
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| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_84 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
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| fifo | StreamFifo_3_85 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
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| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 |
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| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
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| cmdArbiter | StreamArbiter_7_80 | 24 | 24 | 0 | 0 | 3 | 0 | 0 | 0 |
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| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_81 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
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| fifo | StreamFifo_3_82 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
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| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
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| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
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| cmdArbiter | StreamArbiter_7 | 21 | 21 | 0 | 0 | 3 | 0 | 0 | 0 |
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| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
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| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
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| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 90 | 90 | 0 | 0 | 25 | 0 | 0 | 0 |
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| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 74 | 74 | 0 | 0 | 12 | 0 | 0 | 0 |
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| errorSlave | Axi4ReadOnlyErrorSlave_1_79 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
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| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
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| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
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| errorSlave | Axi4WriteOnlyErrorSlave_1_78 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
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| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 52 | 52 | 0 | 0 | 17 | 0 | 0 | 0 |
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| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 36 | 36 | 0 | 0 | 8 | 0 | 0 | 0 |
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| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
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| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 23 | 23 | 0 | 0 | 14 | 0 | 0 | 0 |
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| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 15 | 15 | 0 | 0 | 12 | 0 | 0 | 0 |
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| errorSlave | Axi4WriteOnlyErrorSlave_1 | 8 | 8 | 0 | 0 | 2 | 0 | 0 | 0 |
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| u_Axi_CDC | Axi_CDC | 427 | 299 | 128 | 0 | 317 | 0 | 0 | 0 |
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| arFifo | StreamFifoCC_3_58 | 192 | 156 | 36 | 0 | 77 | 0 | 0 | 0 |
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| (arFifo) | StreamFifoCC_3_58 | 186 | 150 | 36 | 0 | 65 | 0 | 0 | 0 |
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| popToPushGray_buffercc | BufferCC_9_73 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
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| pushToPopGray_buffercc | BufferCC_11_74 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
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| awFifo | StreamFifoCC_59 | 110 | 74 | 36 | 0 | 79 | 0 | 0 | 0 |
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| (awFifo) | StreamFifoCC_59 | 103 | 67 | 36 | 0 | 65 | 0 | 0 | 0 |
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| bufferCC_12 | BufferCC_10_70 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
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| popToPushGray_buffercc | BufferCC_9_71 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
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| pushToPopGray_buffercc | BufferCC_11_72 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
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| bFifo | StreamFifoCC_2_60 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
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| (bFifo) | StreamFifoCC_2_60 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
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| bufferCC_12 | BufferCC_5_67 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
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| popToPushGray_buffercc | BufferCC_4_68 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
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| pushToPopGray_buffercc | BufferCC_6_69 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
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| rFifo | StreamFifoCC_4_61 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
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| (rFifo) | StreamFifoCC_4_61 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
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| popToPushGray_buffercc | BufferCC_65 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
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| pushToPopGray_buffercc | BufferCC_1_66 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
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| wFifo | StreamFifoCC_1_62 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
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| (wFifo) | StreamFifoCC_1_62 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
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| popToPushGray_buffercc | BufferCC_7_63 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
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| pushToPopGray_buffercc | BufferCC_8_64 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
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| u_axi_axil_adapter | axi_axil_adapter | 1245 | 1245 | 0 | 0 | 161 | 0 | 0 | 0 |
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| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 640 | 640 | 0 | 0 | 81 | 0 | 0 | 0 |
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| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 605 | 605 | 0 | 0 | 80 | 0 | 0 | 0 |
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| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 |
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| u_axi_ram | axi_wrap_ram_sp_external | 356 | 356 | 0 | 0 | 78 | 0 | 0 | 0 |
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| u_axi_sram_sp | axi2sram_sp_external | 356 | 356 | 0 | 0 | 78 | 0 | 0 | 0 |
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| u_axi_uart_controller | axi_uart_controller | 684 | 668 | 16 | 0 | 457 | 0 | 0 | 0 |
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| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
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| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
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| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
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| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 |
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| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
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| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
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| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
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| u_cdma_matmul_bridge | cdma_matmul_bridge | 248 | 248 | 0 | 0 | 578 | 0 | 0 | 0 |
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| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
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| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
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| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
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| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
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| u_cpu | core_top | 8584 | 8284 | 300 | 0 | 5591 | 0 | 20 | 0 |
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| (u_cpu) | core_top | 561 | 513 | 48 | 0 | 1 | 0 | 0 | 0 |
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| addr_trans | addr_trans | 2240 | 2100 | 140 | 0 | 1244 | 0 | 0 | 0 |
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| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
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| tlb_entry | tlb_entry | 2240 | 2100 | 140 | 0 | 1204 | 0 | 0 | 0 |
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| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 |
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| btb | btb | 1041 | 961 | 80 | 0 | 1611 | 0 | 0 | 0 |
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| (btb) | btb | 1039 | 959 | 80 | 0 | 1611 | 0 | 0 | 0 |
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| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
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| dcache | dcache | 551 | 519 | 32 | 0 | 146 | 0 | 10 | 0 |
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| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 |
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| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_46 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_47 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_48 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_49 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_50 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_51 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_52 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_53 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
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| lfsr | lfsr_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
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| tagv_ram_way[0].u | tagv_sram_55 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
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| tagv_ram_way[1].u | tagv_sram_56 | 42 | 42 | 0 | 0 | 0 | 0 | 1 | 0 |
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| exe_stage | exe_stage | 666 | 666 | 0 | 0 | 233 | 0 | 0 | 0 |
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| (exe_stage) | exe_stage | 635 | 635 | 0 | 0 | 233 | 0 | 0 | 0 |
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| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
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| icache | icache | 233 | 233 | 0 | 0 | 55 | 0 | 10 | 0 |
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| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
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| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_38 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_39 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_40 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_41 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_42 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_43 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
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| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_44 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
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| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
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| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
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| tagv_ram_way[1].u | tagv_sram_45 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
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| id_stage | id_stage | 1054 | 1054 | 0 | 0 | 108 | 0 | 0 | 0 |
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| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 |
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| mem_stage | mem_stage | 115 | 115 | 0 | 0 | 211 | 0 | 0 | 0 |
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| u_csr | csr | 201 | 201 | 0 | 0 | 663 | 0 | 0 | 0 |
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| u_div | div | 141 | 141 | 0 | 0 | 107 | 0 | 0 | 0 |
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| u_mul | mul | 938 | 938 | 0 | 0 | 592 | 0 | 0 | 0 |
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| wb_stage | wb_stage | 682 | 682 | 0 | 0 | 233 | 0 | 0 | 0 |
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| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 30142 | 28868 | 112 | 1162 | 18251 | 10 | 18 | 0 |
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| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 |
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| u_fft_controller | fft_controller | 6934 | 5894 | 0 | 1040 | 1083 | 8 | 4 | 0 |
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| (u_fft_controller) | fft_controller | 118 | 118 | 0 | 0 | 100 | 0 | 0 | 0 |
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| u_FFT | FFT | 6782 | 5742 | 0 | 1040 | 983 | 8 | 0 | 0 |
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| SU1 | SdfUnit | 2144 | 1376 | 0 | 768 | 197 | 2 | 0 | 0 |
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| SU2 | SdfUnit__parameterized0 | 1567 | 1375 | 0 | 192 | 197 | 2 | 0 | 0 |
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| SU3 | SdfUnit__parameterized1 | 1416 | 1368 | 0 | 48 | 197 | 2 | 0 | 0 |
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| SU4 | SdfUnit__parameterized2 | 1397 | 1365 | 0 | 32 | 197 | 2 | 0 | 0 |
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| SU5 | SdfUnit__parameterized3 | 258 | 258 | 0 | 0 | 195 | 0 | 0 | 0 |
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| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_in1 | my_bram0_21 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_out0 | my_bram0_22 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_out1 | my_bram0_23 | 32 | 32 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_mlkem_axi_cdc | Axi_CDC_5 | 336 | 224 | 112 | 0 | 272 | 0 | 0 | 0 |
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| arFifo | StreamFifoCC_3 | 50 | 22 | 28 | 0 | 55 | 0 | 0 | 0 |
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| (arFifo) | StreamFifoCC_3 | 42 | 14 | 28 | 0 | 43 | 0 | 0 | 0 |
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| popToPushGray_buffercc | BufferCC_9_19 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
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| pushToPopGray_buffercc | BufferCC_11_20 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
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| awFifo | StreamFifoCC | 39 | 15 | 24 | 0 | 49 | 0 | 0 | 0 |
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| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 |
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| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
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| popToPushGray_buffercc | BufferCC_9 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 |
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| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
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| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 |
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| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 |
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| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
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| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
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| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
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| rFifo | StreamFifoCC_4 | 65 | 37 | 28 | 0 | 72 | 0 | 0 | 0 |
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| (rFifo) | StreamFifoCC_4 | 58 | 30 | 28 | 0 | 56 | 0 | 0 | 0 |
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| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
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| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 |
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| wFifo | StreamFifoCC_1 | 164 | 136 | 28 | 0 | 69 | 0 | 0 | 0 |
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| (wFifo) | StreamFifoCC_1 | 159 | 131 | 28 | 0 | 53 | 0 | 0 | 0 |
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| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
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| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
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| u_mlkem_axi_slave | mlkem_axi_slave | 22873 | 22751 | 0 | 122 | 16890 | 2 | 14 | 0 |
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| (u_mlkem_axi_slave) | mlkem_axi_slave | 1179 | 1179 | 0 | 0 | 1064 | 0 | 0 | 0 |
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| u_mlkem | mlkem_top | 21697 | 21575 | 0 | 122 | 15826 | 2 | 14 | 0 |
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| (u_mlkem) | mlkem_top | 2633 | 2633 | 0 | 0 | 5010 | 0 | 0 | 0 |
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| u_bank_a | sd_bram__parameterized0 | 61 | 61 | 0 | 0 | 0 | 1 | 1 | 0 |
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| u_bank_se | sd_bram__parameterized1 | 77 | 77 | 0 | 0 | 0 | 1 | 0 | 0 |
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| u_bank_t | sd_bram__parameterized2 | 632 | 632 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_c_in_bram | sd_bram | 1301 | 1301 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_cbd | sample_cbd_sync_shared | 2739 | 2739 | 0 | 0 | 3186 | 0 | 0 | 0 |
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| u_comp | comp_decomp_sync | 620 | 618 | 0 | 2 | 319 | 0 | 0 | 0 |
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| u_ct_bram | sd_bram_6 | 10 | 10 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_dkp_bram | sd_bram_7 | 74 | 74 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_ek_bram | sd_bram_8 | 304 | 304 | 0 | 0 | 0 | 0 | 1 | 0 |
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| u_keccak | keccak_core | 5258 | 5258 | 0 | 0 | 1618 | 0 | 0 | 0 |
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| u_ntt | ntt_core | 1900 | 1817 | 0 | 83 | 1062 | 0 | 4 | 0 |
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| u_pmul | poly_mul_sync | 2058 | 2021 | 0 | 37 | 584 | 0 | 4 | 0 |
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| u_sha3 | sha3_top_shared | 1955 | 1955 | 0 | 0 | 2378 | 0 | 0 | 0 |
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| u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 |
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| u_matmul_axi_slave | matmul_axi_slave | 9879 | 9697 | 176 | 6 | 3243 | 0 | 0 | 0 |
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| (u_matmul_axi_slave) | matmul_axi_slave | 5761 | 5579 | 176 | 6 | 2475 | 0 | 0 | 0 |
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| mult_inst[0].u_mult | pipelined_mult_32x32 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 |
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| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 999 | 999 | 0 | 0 | 192 | 0 | 0 | 0 |
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| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1060 | 1060 | 0 | 0 | 192 | 0 | 0 | 0 |
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| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 |
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| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1557 | 1557 | 0 | 0 | 1476 | 0 | 1 | 0 |
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| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 600 | 600 | 0 | 0 | 1180 | 0 | 0 | 0 |
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| u_core_engine | snix_axi_mm2mm | 960 | 960 | 0 | 0 | 296 | 0 | 1 | 0 |
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| (u_core_engine) | snix_axi_mm2mm | 750 | 750 | 0 | 0 | 243 | 0 | 0 | 0 |
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| axis_fifo_u0 | snix_axis_fifo | 210 | 210 | 0 | 0 | 53 | 0 | 1 | 0 |
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| u_fifo | snix_sync_fifo | 210 | 210 | 0 | 0 | 53 | 0 | 1 | 0 |
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+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
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* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
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