141 lines
5.0 KiB
C
141 lines
5.0 KiB
C
/**
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* user-sample - CIC-IEC 2026 Stage 3 Evaluation Program
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*
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* (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE v2)
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*
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* Optimizations over v1:
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* 1. Pre-fire DMA Ch0 load at loop tail → fully overlaps with IP compute
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* 2. Inlined wait loops → zero function-call overhead in hot path
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* 3. Inlined DMA start → skips redundant STATUS_BUSY_BIT check
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* 4. XOR bank toggle → avoids g%2 recomputation per iteration
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*/
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#include <dma.h>
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#include <confreg_time.h>
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/* ─── UART 16550 direct access (bypasses slow printf/picolibc) ──────── */
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#define UART_THR (*(volatile unsigned char *)0xbf000000)
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#define UART_LSR (*(volatile unsigned char *)0xbf000005)
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#define LSR_THRE 0x20
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static inline void uart_tx(unsigned char c) {
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while (!(UART_LSR & LSR_THRE)) {}
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UART_THR = c;
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}
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static void uart_puts(const char *s) {
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while (*s) uart_tx(*s++);
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}
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static void uart_puthex(unsigned int val) {
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int i;
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for (i = 28; i >= 0; i -= 4) {
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unsigned char nibble = (val >> i) & 0xF;
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uart_tx(nibble < 10 ? '0' + nibble : 'a' + nibble - 10);
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}
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}
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static void uart_putdec(unsigned int val) {
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char buf[10];
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int i = 0;
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if (val == 0) {
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uart_tx('0');
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return;
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}
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while (val != 0) {
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buf[i++] = (char)('0' + (val % 10));
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val /= 10;
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}
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while (i > 0) {
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uart_tx((unsigned char)buf[--i]);
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}
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}
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/* ─── Configurable group count (default 5000) ──────────────────────── */
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#ifndef MATMUL_GROUP_NUM
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#define MATMUL_GROUP_NUM 5000
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#endif
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/* ─── BSP globals ─────────────────────────────────────────────────── */
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unsigned long UART_BASE = 0xbf000000;
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unsigned long CONFREG_TIMER_BASE = 0xbf20f100;
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unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L;
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unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
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/* ─── Memory layout ────────────────────────────────────────────────── */
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#define EXTRAM_BASE_PHYS 0x1c400000
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#define EXTRAM_BASE_UNCACHED (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF))
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#define SRC_BASE_WORDS 0
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#define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32)
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#define RESULT_WORDS (MATMUL_GROUP_NUM * 48)
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/* ExtRAM Physical Addresses for DMA */
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#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4) + (g) * 128)
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#define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4) + (g) * 192)
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/* ─── MATMUL IP registers (Ping-Pong Memory Map) ──────────────────── */
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#define MATMUL_BASE_PHYS 0x1f500000
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#define MATMUL_BASE_UNCACHED 0xbf500000
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#define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000)
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#define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004)
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#define MATMUL_BASE_PHYS_FOR_DMA MATMUL_BASE_PHYS
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#define CTRL_START_B0 0x1
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#define CTRL_START_B1 0x2
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#define STATUS_DONE 0x2
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#define STATUS_ERROR 0x4
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#define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010)
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/* ─── Pre-computed DMA burst control word ──────────────────────────── */
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#define DMA_CTRL_VAL (CTRL_BURST_SIZE(2) | CTRL_BURST_LEN(63) | CTRL_START_BIT)
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#define MATMUL_EP_ID 0
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/* ═══════════════════════════════════════════════════════════════════ */
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int main(void)
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{
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if (MATMUL_GROUP_NUM <= 0) return 0;
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/* ── Hot-path local volatile pointers (one-time addr calc) ──────── */
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volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC;
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volatile dma_seq_regs_t *seq = DMA_SEQ;
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unsigned int crc;
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unsigned int cycle_start, cycle_end, cycles, time_us;
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/* ── Start marker (must be first output) ──────────────────── */
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uart_puts("MATMUL_START\r\n");
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cycle_start = get_clock_count();
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seq->STATUS = SEQ_DONE_BIT;
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seq->SRC_BASE = EXTRAM_PHYS_AB(0);
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seq->DST_BASE = EXTRAM_PHYS_C(0);
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seq->GROUPS = MATMUL_GROUP_NUM;
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seq->MAT_BASE = MATMUL_BASE_PHYS_FOR_DMA;
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seq->SRC_STRIDE = 128;
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seq->DST_STRIDE = 192;
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seq->CTRL = SEQ_START_BIT;
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while (!(seq->STATUS & SEQ_DONE_BIT)) {}
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seq->STATUS = SEQ_DONE_BIT;
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cycle_end = get_clock_count();
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cycles = cycle_end - cycle_start;
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time_us = cycles / (CORE_CLOCKS_PER_SEC / 1000000UL);
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/* ── Read hardware CRC32 ──────────────────────────────────── */
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crc = *mat_crc;
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uart_puts("MATMUL_CRC32=");
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uart_puthex(crc);
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uart_puts("\r\nMATMUL_CYCLES=");
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uart_putdec(cycles);
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uart_puts("\r\nMATMUL_TIME_US=");
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uart_putdec(time_us);
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uart_puts("\r\nMATMUL_DONE\r\n");
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return 0;
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}
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