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ciciec2026/fpga/vivado_reports_withdsp
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FallenSigh f676fc6e60 add vivado reports
2026-07-08 03:48:37 +08:00
..
clock_interaction.rpt
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2026-07-08 03:48:37 +08:00
clocks.rpt
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2026-07-08 03:48:37 +08:00
design_analysis_complexity.rpt
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2026-07-08 03:48:37 +08:00
design_analysis_timing.rpt
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2026-07-08 03:48:37 +08:00
drc.rpt
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2026-07-08 03:48:37 +08:00
high_fanout.rpt
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2026-07-08 03:48:37 +08:00
methodology.rpt
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2026-07-08 03:48:37 +08:00
mlkem_clk_timing.rpt
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power.rpt
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resource.png
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2026-07-08 03:48:37 +08:00
route_status.rpt
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timing_hold_paths.rpt
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2026-07-08 03:48:37 +08:00
timing_setup_paths.rpt
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timing_summary_full.rpt
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2026-07-08 03:48:37 +08:00
timing_summary_hold_full.rpt
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2026-07-08 03:48:37 +08:00
utilization_hier.rpt
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2026-07-08 03:48:37 +08:00
utilization.rpt
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2026-07-08 03:48:37 +08:00