ciciec2026

fallensigh/ciciec2026

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FallenSigh b2c8d6eaf3 perf(mlkem): move poly_mul coeff storage to even/odd banked BRAM

Replace poly_mul_sync's two 256x12 LUT register arrays (mem_A/mem_B, ~8k LUT)
with four sd_bram banks (A_even/A_odd/B_even/B_odd, 128x12). The base-case
reads mem[2k] and mem[2k+1] together, so an even/odd split gives each bank a
single read port. This removes the multi-port LUT mux and the long
BRAM->register-file route that was the mlkem_clk critical path.

sd_bram reads are synchronous (1-cycle); the existing 2-cycle issue cadence
absorbs it (address on the gap cycle, data on the issue cycle), with a
one-cycle priming gap at LOAD->RUN. Interface and behavior unchanged.

Verified byte-exact vs NIST KAT: poly_mul standalone TB 11/11, Encaps 9/9,
Decaps 9/9 (incl. reject + DECOMP), KeyGen, hello_world e2e — all PASS.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

2026-07-11 05:41:27 +08:00

common

feat: add ML-KEM accelerator with AXI slave wrapper

2026-06-30 01:39:35 +08:00

comp_decomp

perf(mlkem): stream compress feed (B1) — ~27% fewer Encaps cycles

2026-07-11 02:00:03 +08:00

ntt

perf(mlkem): move NTT coeff storage to 4-way banked BRAM

2026-07-11 05:16:58 +08:00

poly_arith

feat: add ML-KEM accelerator with AXI slave wrapper